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soc/interconnect/wishbonebridge: fix import
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@ -5,7 +5,7 @@ from litex.gen.genlib.record import Record
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from litex.gen.genlib.fsm import FSM, NextState
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.stream import Sink, Source
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from litex.soc.interconnect import stream
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class WishboneStreamingBridge(Module):
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