soc_zynq: fix typo

2019-09-05 15:55:18 +02:00 · 2019-09-05 15:55:18 +02:00 · 9051cf97e4
parent 67a09aef05
commit 9051cf97e4
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@ -23,7 +23,7 @@ def axi_fifo_ctrl_layout():
        ("wrissuecapen",    1, DIR_S_TO_M),
    ]

-# SoC Zync -----------------------------------------------------------------------------------------
+# SoC Zynq -----------------------------------------------------------------------------------------

 class SoCZynq(SoCCore):
    SoCCore.mem_map["csr"] = 0x00000000