Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc_sdram: remove use_full_memory_we parameter (always used as True)

This commit is contained in:
Florent Kermarrec 2019-11-07 08:56:52 +01:00
parent 1b94699d12
commit 9053d0803a
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/soc/integration/soc_sdram.py
View File

@ -42,7 +42,7 @@ class SoCSDRAM(SoCCore):
raise FinalizeError raise FinalizeError
self._wb_sdram_ifs.append(interface) self._wb_sdram_ifs.append(interface)
def register_sdram(self, phy, geom_settings, timing_settings, use_full_memory_we=True, **kwargs): def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
assert not self._sdram_phy assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
@ -99,7 +99,7 @@ class SoCSDRAM(SoCCore):
# XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
from litex.build.xilinx.vivado import XilinxVivadoToolchain from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we: if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache) self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else: else: