bios/sdram: improve write/read leveling
write_leveling: select last 0 to 1 transition. read_leveling: do it by module (select best bitslip for each module)
This commit is contained in:
parent
deffa60324
commit
915c2f417a
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@ -207,6 +207,8 @@ void sdrwr(char *startaddr)
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#endif
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#endif
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#define ERR_DDRPHY_BITSLIP 8
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#define ERR_DDRPHY_BITSLIP 8
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#define NBMODULES DFII_PIX_DATA_SIZE/2
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#ifdef CSR_DDRPHY_WLEVEL_EN_ADDR
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#ifdef CSR_DDRPHY_WLEVEL_EN_ADDR
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void sdrwlon(void)
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void sdrwlon(void)
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@ -238,22 +240,20 @@ int write_level(void)
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int one_window_active;
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int one_window_active;
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int one_window_start;
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int one_window_start;
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int one_window_len;
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int best_one_window_len;
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int delays[DFII_PIX_DATA_SIZE/2];
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int delays[NBMODULES];
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int ok;
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int ok;
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err_ddrphy_wdly = ERR_DDRPHY_DELAY - ddrphy_half_sys8x_taps_read();
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err_ddrphy_wdly = ERR_DDRPHY_DELAY - ddrphy_half_sys8x_taps_read();
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printf("Write leveling scan:\n");
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printf("Write leveling:\n");
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sdrwlon();
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sdrwlon();
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cdelay(100);
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cdelay(100);
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for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) {
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for(i=0;i<NBMODULES;i++) {
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printf("m%d: ", i);
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printf("m%d: |", i);
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dq_address = sdram_dfii_pix_rddata_addr[0]+4*(DFII_PIX_DATA_SIZE/2-1-i);
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dq_address = sdram_dfii_pix_rddata_addr[0]+4*(NBMODULES-1-i);
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/* reset delay */
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/* reset delay */
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ddrphy_dly_sel_write(1 << i);
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ddrphy_dly_sel_write(1 << i);
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@ -274,24 +274,16 @@ int write_level(void)
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ddrphy_wdly_dqs_inc_write(1);
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ddrphy_wdly_dqs_inc_write(1);
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cdelay(10);
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cdelay(10);
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}
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}
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printf("\n");
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printf("|");
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/* find best delay */
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/* select last 0/1 transition */
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one_window_active = 0;
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one_window_active = 0;
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one_window_start = 0;
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one_window_start = 0;
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one_window_len = 0;
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best_one_window_len = 0;
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delays[i] = -1;
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delays[i] = -1;
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for(j=0;j<err_ddrphy_wdly;j++) {
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for(j=0;j<err_ddrphy_wdly;j++) {
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if (one_window_active) {
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if (one_window_active) {
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if ((taps_scan[j] == 0) || (j == err_ddrphy_wdly-1)) {
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if (taps_scan[j] == 0)
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one_window_len = j - one_window_start;
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if (one_window_len > best_one_window_len) {
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delays[i] = one_window_start;
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best_one_window_len = one_window_len;
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}
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one_window_active = 0;
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one_window_active = 0;
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}
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} else {
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} else {
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if (taps_scan[j]) {
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if (taps_scan[j]) {
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one_window_active = 1;
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one_window_active = 1;
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@ -299,6 +291,7 @@ int write_level(void)
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}
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}
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}
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}
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}
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}
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delays[i] = one_window_start;
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/* configure delays */
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/* configure delays */
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ddrphy_wdly_dq_rst_write(1);
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ddrphy_wdly_dq_rst_write(1);
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@ -311,23 +304,18 @@ int write_level(void)
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ddrphy_wdly_dq_inc_write(1);
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ddrphy_wdly_dq_inc_write(1);
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ddrphy_wdly_dqs_inc_write(1);
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ddrphy_wdly_dqs_inc_write(1);
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}
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}
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printf(" delay: %02d\n", delays[i]);
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}
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}
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sdrwloff();
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sdrwloff();
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ok = 1;
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ok = 1;
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printf("Write leveling: ");
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for(i=NBMODULES-1;i>=0;i--) {
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for(i=DFII_PIX_DATA_SIZE/2-1;i>=0;i--) {
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printf("%2d ", delays[i]);
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if(delays[i] < 0)
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if(delays[i] < 0)
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ok = 0;
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ok = 0;
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}
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}
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if(ok)
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printf("completed\n");
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else
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printf("failed\n");
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return ok;
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return ok;
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}
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}
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@ -346,16 +334,13 @@ static void read_bitslip_inc(char m)
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#endif
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#endif
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}
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}
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static int read_level_scan(int silent)
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static int read_level_scan(int module, int silent)
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{
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{
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unsigned int prv;
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unsigned int prv;
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unsigned char prs[DFII_NPHASES*DFII_PIX_DATA_SIZE];
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unsigned char prs[DFII_NPHASES*DFII_PIX_DATA_SIZE];
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int p, i, j;
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int p, i, j;
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int score;
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int score;
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if (!silent)
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printf("Read delays scan:\n");
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/* Generate pseudo-random sequence */
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/* Generate pseudo-random sequence */
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prv = 42;
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prv = 42;
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for(i=0;i<DFII_NPHASES*DFII_PIX_DATA_SIZE;i++) {
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for(i=0;i<DFII_NPHASES*DFII_PIX_DATA_SIZE;i++) {
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@ -381,30 +366,29 @@ static int read_level_scan(int silent)
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sdram_dfii_pird_address_write(0);
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sdram_dfii_pird_address_write(0);
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sdram_dfii_pird_baddress_write(0);
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sdram_dfii_pird_baddress_write(0);
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score = 0;
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score = 0;
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for(i=DFII_PIX_DATA_SIZE/2-1;i>=0;i--) {
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if (!silent)
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if (!silent)
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printf("m%d: ", (DFII_PIX_DATA_SIZE/2-i-1));
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printf("m%d: |", module);
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ddrphy_dly_sel_write(1 << (DFII_PIX_DATA_SIZE/2-i-1));
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ddrphy_dly_sel_write(1 << module);
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ddrphy_rdly_dq_rst_write(1);
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ddrphy_rdly_dq_rst_write(1);
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for(j=0; j<ERR_DDRPHY_DELAY;j++) {
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for(j=0; j<ERR_DDRPHY_DELAY;j++) {
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int working;
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int working;
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command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
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command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
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cdelay(15);
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cdelay(15);
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working = 1;
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working = 1;
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for(p=0;p<DFII_NPHASES;p++) {
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for(p=0;p<DFII_NPHASES;p++) {
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+(NBMODULES-module-1)])
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working = 0;
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working = 0;
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1])
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working = 0;
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working = 0;
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}
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if (!silent)
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printf("%d", working);
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score += working;
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ddrphy_rdly_dq_inc_write(1);
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}
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}
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if (!silent)
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if (!silent)
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printf("\n");
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printf("%d", working);
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score += working;
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ddrphy_rdly_dq_inc_write(1);
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}
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}
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if (!silent)
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printf("|");
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/* Precharge */
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/* Precharge */
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sdram_dfii_pi0_address_write(0);
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sdram_dfii_pi0_address_write(0);
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@ -415,7 +399,7 @@ static int read_level_scan(int silent)
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return score;
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return score;
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}
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}
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static void read_level(void)
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static void read_level(int module)
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{
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{
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unsigned int prv;
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unsigned int prv;
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unsigned char prs[DFII_NPHASES*DFII_PIX_DATA_SIZE];
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unsigned char prs[DFII_NPHASES*DFII_PIX_DATA_SIZE];
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@ -423,7 +407,7 @@ static void read_level(void)
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int working;
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int working;
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int delay, delay_min, delay_max;
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int delay, delay_min, delay_max;
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printf("Read delays: ");
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printf("delays: ");
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/* Generate pseudo-random sequence */
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/* Generate pseudo-random sequence */
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prv = 42;
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prv = 42;
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@ -449,77 +433,74 @@ static void read_level(void)
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/* Calibrate each DQ in turn */
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/* Calibrate each DQ in turn */
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sdram_dfii_pird_address_write(0);
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sdram_dfii_pird_address_write(0);
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sdram_dfii_pird_baddress_write(0);
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sdram_dfii_pird_baddress_write(0);
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for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) {
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ddrphy_dly_sel_write(1 << (DFII_PIX_DATA_SIZE/2-i-1));
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delay = 0;
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/* Find smallest working delay */
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ddrphy_dly_sel_write(1 << module);
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ddrphy_rdly_dq_rst_write(1);
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delay = 0;
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while(1) {
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command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
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cdelay(15);
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working = 1;
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for(p=0;p<DFII_NPHASES;p++) {
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
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working = 0;
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
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working = 0;
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}
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if(working)
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break;
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delay++;
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if(delay >= ERR_DDRPHY_DELAY)
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break;
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ddrphy_rdly_dq_inc_write(1);
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}
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delay_min = delay;
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/* Get a bit further into the working zone */
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/* Find smallest working delay */
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#ifdef KUSDDRPHY
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ddrphy_rdly_dq_rst_write(1);
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for(j=0;j<16;j++) {
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while(1) {
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delay += 1;
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command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
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ddrphy_rdly_dq_inc_write(1);
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cdelay(15);
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working = 1;
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for(p=0;p<DFII_NPHASES;p++) {
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+(NBMODULES-module-1)])
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working = 0;
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1])
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working = 0;
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}
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}
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#else
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if(working)
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break;
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delay++;
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delay++;
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if(delay >= ERR_DDRPHY_DELAY)
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break;
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ddrphy_rdly_dq_inc_write(1);
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ddrphy_rdly_dq_inc_write(1);
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}
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delay_min = delay;
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/* Get a bit further into the working zone */
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#ifdef KUSDDRPHY
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for(j=0;j<16;j++) {
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delay += 1;
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ddrphy_rdly_dq_inc_write(1);
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}
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#else
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delay++;
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ddrphy_rdly_dq_inc_write(1);
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#endif
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#endif
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/* Find largest working delay */
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/* Find largest working delay */
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while(1) {
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while(1) {
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command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
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command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
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cdelay(15);
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cdelay(15);
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working = 1;
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working = 1;
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for(p=0;p<DFII_NPHASES;p++) {
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for(p=0;p<DFII_NPHASES;p++) {
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*i) != prs[DFII_PIX_DATA_SIZE*p+i])
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+(NBMODULES-module-1)])
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working = 0;
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working = 0;
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(i+DFII_PIX_DATA_SIZE/2)) != prs[DFII_PIX_DATA_SIZE*p+i+DFII_PIX_DATA_SIZE/2])
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if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1])
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working = 0;
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working = 0;
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}
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if(!working)
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break;
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delay++;
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if(delay >= ERR_DDRPHY_DELAY)
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break;
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ddrphy_rdly_dq_inc_write(1);
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}
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}
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delay_max = delay;
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if(!working)
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break;
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printf("%d:%02d-%02d ", DFII_PIX_DATA_SIZE/2-i-1, delay_min, delay_max);
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delay++;
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if(delay >= ERR_DDRPHY_DELAY)
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/* Set delay to the middle */
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break;
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ddrphy_rdly_dq_rst_write(1);
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ddrphy_rdly_dq_inc_write(1);
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for(j=0;j<(delay_min+delay_max)/2;j++)
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ddrphy_rdly_dq_inc_write(1);
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}
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}
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delay_max = delay;
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printf("%02d+-%02d", (delay_min+delay_max)/2, (delay_max-delay_min)/2);
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/* Set delay to the middle */
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ddrphy_rdly_dq_rst_write(1);
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for(j=0;j<(delay_min+delay_max)/2;j++)
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ddrphy_rdly_dq_inc_write(1);
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/* Precharge */
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/* Precharge */
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sdram_dfii_pi0_address_write(0);
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sdram_dfii_pi0_address_write(0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(15);
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cdelay(15);
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printf("completed\n");
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}
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}
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#endif /* CSR_DDRPHY_BASE */
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#endif /* CSR_DDRPHY_BASE */
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@ -566,7 +547,7 @@ static int memtest_bus(void)
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if(rdata != ONEZERO) {
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if(rdata != ONEZERO) {
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errors++;
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errors++;
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#ifdef MEMTEST_BUS_DEBUG
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#ifdef MEMTEST_BUS_DEBUG
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printf("[bus: %0x]: %08x vs %08x\n", i, rdata, ONEZERO);
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printf("[bus: 0x%0x]: 0x%08x vs 0x%08x\n", i, rdata, ONEZERO);
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#endif
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#endif
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}
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}
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}
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}
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@ -581,7 +562,7 @@ static int memtest_bus(void)
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if(rdata != ZEROONE) {
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if(rdata != ZEROONE) {
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errors++;
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errors++;
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#ifdef MEMTEST_BUS_DEBUG
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#ifdef MEMTEST_BUS_DEBUG
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printf("[bus %0x]: %08x vs %08x\n", i, rdata, ZEROONE);
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printf("[bus 0x%0x]: 0x%08x vs 0x%08x\n", i, rdata, ZEROONE);
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#endif
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#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -620,7 +601,7 @@ static int memtest_data(void)
|
||||||
if(rdata != seed_32) {
|
if(rdata != seed_32) {
|
||||||
errors++;
|
errors++;
|
||||||
#ifdef MEMTEST_DATA_DEBUG
|
#ifdef MEMTEST_DATA_DEBUG
|
||||||
printf("[data %0x]: %08x vs %08x\n", i, rdata, seed_32);
|
printf("[data 0x%0x]: 0x%08x vs 0x%08x\n", i, rdata, seed_32);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -658,7 +639,7 @@ static int memtest_addr(void)
|
||||||
if(rdata != i) {
|
if(rdata != i) {
|
||||||
errors++;
|
errors++;
|
||||||
#ifdef MEMTEST_ADDR_DEBUG
|
#ifdef MEMTEST_ADDR_DEBUG
|
||||||
printf("[addr %0x]: %08x vs %08x\n", i, rdata, i);
|
printf("[addr 0x%0x]: 0x%08x vs 0x%08x\n", i, rdata, i);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -701,7 +682,7 @@ int sdrlevel(int silent)
|
||||||
|
|
||||||
sdrsw();
|
sdrsw();
|
||||||
|
|
||||||
for(i=0; i<DFII_PIX_DATA_SIZE/2; i++) {
|
for(i=0; i<NBMODULES; i++) {
|
||||||
ddrphy_dly_sel_write(1<<i);
|
ddrphy_dly_sel_write(1<<i);
|
||||||
ddrphy_rdly_dq_rst_write(1);
|
ddrphy_rdly_dq_rst_write(1);
|
||||||
ddrphy_rdly_dq_bitslip_rst_write(1);
|
ddrphy_rdly_dq_bitslip_rst_write(1);
|
||||||
|
@ -712,38 +693,36 @@ int sdrlevel(int silent)
|
||||||
return 0;
|
return 0;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* scan possible read windows */
|
printf("Read leveling:\n");
|
||||||
best_score = 0;
|
for(i=0; i<NBMODULES; i++) {
|
||||||
best_bitslip = 0;
|
/* scan possible read windows */
|
||||||
for(bitslip=0; bitslip<ERR_DDRPHY_BITSLIP; bitslip++) {
|
best_score = 0;
|
||||||
if (!silent)
|
best_bitslip = 0;
|
||||||
printf("Read bitslip: %d\n", bitslip);
|
for(bitslip=0; bitslip<ERR_DDRPHY_BITSLIP; bitslip++) {
|
||||||
/* compute score */
|
/* compute score */
|
||||||
score = read_level_scan(silent);
|
score = read_level_scan(i, silent);
|
||||||
if (score > best_score) {
|
if (score > best_score) {
|
||||||
best_bitslip = bitslip;
|
best_bitslip = bitslip;
|
||||||
best_score = score;
|
best_score = score;
|
||||||
}
|
}
|
||||||
/* exit */
|
/* exit */
|
||||||
if (bitslip == ERR_DDRPHY_BITSLIP-1)
|
if (bitslip == ERR_DDRPHY_BITSLIP-1)
|
||||||
break;
|
break;
|
||||||
/* increment bitslip */
|
/* increment bitslip */
|
||||||
for(i=0; i<DFII_PIX_DATA_SIZE/2; i++)
|
|
||||||
read_bitslip_inc(i);
|
read_bitslip_inc(i);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* select best read window */
|
/* select best read window */
|
||||||
printf("Best read bitslip: %d\n", best_bitslip);
|
|
||||||
for(i=0; i<DFII_PIX_DATA_SIZE/2; i++) {
|
|
||||||
ddrphy_dly_sel_write(1<<i);
|
|
||||||
ddrphy_rdly_dq_bitslip_rst_write(1);
|
ddrphy_rdly_dq_bitslip_rst_write(1);
|
||||||
for (j=0; j<best_bitslip; j++)
|
for (j=0; j<best_bitslip; j++)
|
||||||
read_bitslip_inc(i);
|
read_bitslip_inc(i);
|
||||||
}
|
|
||||||
|
|
||||||
/* show scan and do leveling */
|
/* show scan and do leveling */
|
||||||
read_level_scan(0);
|
read_level_scan(i, 0);
|
||||||
read_level();
|
printf(" bitslip:%d ", best_bitslip);
|
||||||
|
read_level(i);
|
||||||
|
printf("\n");
|
||||||
|
}
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
@ -765,10 +744,6 @@ int sdrinit(void)
|
||||||
#endif
|
#endif
|
||||||
sdrhw();
|
sdrhw();
|
||||||
if(!memtest()) {
|
if(!memtest()) {
|
||||||
#ifdef CSR_DDRPHY_BASE
|
|
||||||
/* show scans */
|
|
||||||
sdrlevel(0);
|
|
||||||
#endif
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue