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cores/uart: cleanup

This commit is contained in:
Florent Kermarrec 2020-02-28 22:11:51 +01:00
parent ea8563339f
commit 9199306a65
1 changed files with 20 additions and 20 deletions
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12
litex/soc/cores/uart.py
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@ -1,5 +1,5 @@
# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk> # This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk> # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
# This file is Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro> # This file is Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
# License: BSD # License: BSD
@ -38,13 +38,13 @@ class RS232PHYRX(Module):
phase_accumulator_rx = Signal(32) phase_accumulator_rx = Signal(32)
rx = Signal() rx = Signal()
self.specials += MultiReg(pads.rx, rx)
rx_r = Signal() rx_r = Signal()
rx_reg = Signal(8) rx_reg = Signal(8)
rx_bitcount = Signal(4) rx_bitcount = Signal(4)
rx_busy = Signal() rx_busy = Signal()
rx_done = self.source.valid rx_done = self.source.valid
rx_data = self.source.data rx_data = self.source.data
self.specials += MultiReg(pads.rx, rx)
self.sync += [ self.sync += [
rx_done.eq(0), rx_done.eq(0),
rx_r.eq(rx), rx_r.eq(rx),
@ -189,10 +189,10 @@ def UARTPHY(pads, clk_freq, baudrate):
class UART(Module, AutoCSR, UARTInterface): class UART(Module, AutoCSR, UARTInterface):
def __init__(self, phy=None, def __init__(self, phy=None,
tx_fifo_depth=16, tx_fifo_depth = 16,
rx_fifo_depth=16, rx_fifo_depth = 16,
rx_fifo_rx_we=False, rx_fifo_rx_we = False,
phy_cd="sys",): phy_cd = "sys"):
self._rxtx = CSR(8) self._rxtx = CSR(8)
self._txfull = CSRStatus() self._txfull = CSRStatus()
self._rxempty = CSRStatus() self._rxempty = CSRStatus()