soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.

2020-02-28 22:03:40 +01:00 · 2020-02-28 22:03:40 +01:00 · ea8563339f
parent 12a7528667
commit ea8563339f
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@ -272,7 +272,7 @@ class UARTCrossover(UART):
    def __init__(self, **kwargs):
        assert kwargs.get("phy", None) == None
        UART.__init__(self, **kwargs)
-        self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2, rx_fifo_rx_we=True)
+        self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=1, rx_fifo_rx_we=True)
        self.comb += [
            self.source.connect(self.xover.sink),
            self.xover.source.connect(self.sink)