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bank/csrgen: use new bus API

This commit is contained in:
Sebastien Bourdeauducq 2012-02-15 16:42:17 +01:00
parent af5230c8ee
commit 91e279ee04
2 changed files with 14 additions and 14 deletions
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2
examples/simple_gpio.py
View File

@ -18,5 +18,5 @@ bank = csrgen.Bank([oreg, ireg])
f = bank.get_fragment() + inf
oreg.field.r.name_override = "gpio_out"
i = bank.interface
v = verilog.convert(f, {i.d_o, oreg.field.r, i.a_i, i.we_i, i.d_i, gpio_in})
v = verilog.convert(f, {i.dat_r, oreg.field.r, i.adr, i.we, i.dat_w, gpio_in})
print(v)

26
migen/bank/csrgen.py
View File

@ -6,14 +6,14 @@ class Bank:
def __init__(self, description, address=0):
self.description = description
self.address = address
self.interface = Slave()
self.interface = Interface()
def get_fragment(self):
comb = []
sync = []
sel = Signal()
comb.append(sel.eq(self.interface.adr_i[9:] == Constant(self.address, BV(5))))
comb.append(sel.eq(self.interface.adr[9:] == Constant(self.address, BV(5))))
desc_exp = expand_description(self.description, 8)
nbits = bits_for(len(desc_exp)-1)
@ -22,29 +22,29 @@ class Bank:
bwcases = []
for i, reg in enumerate(desc_exp):
if isinstance(reg, RegisterRaw):
comb.append(reg.r.eq(self.interface.dat_i[:reg.size]))
comb.append(reg.r.eq(self.interface.dat_w[:reg.size]))
comb.append(reg.re.eq(sel & \
self.interface.we_i & \
(self.interface.adr_i[:nbits] == Constant(i, BV(nbits)))))
self.interface.we & \
(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
elif isinstance(reg, RegisterFields):
bwra = [Constant(i, BV(nbits))]
offset = 0
for field in reg.fields:
if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
bwra.append(field.storage.eq(self.interface.dat_i[offset:offset+field.size]))
bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
offset += field.size
if len(bwra) > 1:
bwcases.append(bwra)
else:
raise TypeError
if bwcases:
sync.append(If(sel & self.interface.we_i, Case(self.interface.adr_i[:nbits], *bwcases)))
sync.append(If(sel & self.interface.we, Case(self.interface.adr[:nbits], *bwcases)))
# Bus reads
brcases = []
for i, reg in enumerate(desc_exp):
if isinstance(reg, RegisterRaw):
brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(reg.w)])
brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(reg.w)])
elif isinstance(reg, RegisterFields):
brs = []
reg_readable = False
@ -56,16 +56,16 @@ class Bank:
brs.append(Constant(0, BV(field.size)))
if reg_readable:
if len(brs) > 1:
brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(Cat(*brs))])
brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(Cat(*brs))])
else:
brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(brs[0])])
brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(brs[0])])
else:
raise TypeError
if brcases:
sync.append(self.interface.dat_o.eq(Constant(0, BV(8))))
sync.append(If(sel, Case(self.interface.adr_i[:nbits], *brcases)))
sync.append(self.interface.dat_r.eq(Constant(0, BV(8))))
sync.append(If(sel, Case(self.interface.adr[:nbits], *brcases)))
else:
comb.append(self.interface.dat_o.eq(Constant(0, BV(8))))
comb.append(self.interface.dat_r.eq(Constant(0, BV(8))))
# Device access
for reg in self.description: