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wishbone: only send ack to the active master in arbiter

This commit is contained in:
Sebastien Bourdeauducq 2011-12-13 00:25:25 +01:00
parent a72faaecdd
commit 923fc52e68
1 changed files with 6 additions and 2 deletions
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6
migen/bus/wishbone.py
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@ -44,9 +44,14 @@ class Arbiter:
s2m_names = [GetSigName(x, False) for x in _desc if not x[0]] s2m_names = [GetSigName(x, False) for x in _desc if not x[0]]
for name in s2m_names: for name in s2m_names:
source = getattr(self.target, name) source = getattr(self.target, name)
i = 0
for m in self.masters: for m in self.masters:
dest = getattr(m, name) dest = getattr(m, name)
if name == "ack_i" or name == "err_i":
comb.append(f.Assign(dest, source & (self.rr.grant == f.Constant(i, self.rr.grant.bv))))
else:
comb.append(f.Assign(dest, source)) comb.append(f.Assign(dest, source))
i += 1
# connect bus requests to round-robin selector # connect bus requests to round-robin selector
reqs = [m.cyc_o for m in self.masters] reqs = [m.cyc_o for m in self.masters]
@ -54,7 +59,6 @@ class Arbiter:
return f.Fragment(comb) + self.rr.GetFragment() return f.Fragment(comb) + self.rr.GetFragment()
class Decoder: class Decoder:
# slaves is a list of pairs: # slaves is a list of pairs:
# 0) structure.Constant defining address (always decoded on the upper bits) # 0) structure.Constant defining address (always decoded on the upper bits)