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Build your hardware, easily!
43 Commits 40 Branches 14 Tags 26 MiB
C 52.8%
Python 43.5%
Assembly 1.4%
SystemVerilog 1.3%
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Sebastien Bourdeauducq 923fc52e68 wishbone: only send ack to the active master in arbiter 2011-12-13 00:25:25 +01:00
examples Corelogic conversion example 2011-12-08 21:25:05 +01:00
migen wishbone: only send ack to the active master in arbiter 2011-12-13 00:25:25 +01:00
.gitignore Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00