wishbone: decoder: fix slave cyc generation in registered mode

2011-12-13 14:08:39 +01:00 · 2011-12-13 14:08:39 +01:00 · 92f24b784d
parent 0ea7a9b2e6
commit 92f24b784d
1 changed files with 1 additions and 1 deletions
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@ -113,7 +113,7 @@ class Decoder:
 		# combine cyc with slave selection signals
 		i = 0
 		for slave in self.slaves:
-			comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel_r[i]))
+			comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel[i]))
 			i += 1
 		
 		# generate master ack (resp. err) by ORing all slave acks (resp. errs)