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Build your hardware, easily!
45 Commits 40 Branches 14 Tags 51 MiB
C 52.8%
Python 43.5%
Assembly 1.4%
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Sebastien Bourdeauducq 92f24b784d wishbone: decoder: fix slave cyc generation in registered mode 2011-12-13 14:08:39 +01:00
examples Corelogic conversion example 2011-12-08 21:25:05 +01:00
migen wishbone: decoder: fix slave cyc generation in registered mode 2011-12-13 14:08:39 +01:00
.gitignore Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00