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wishbone: decoder: fix slave cyc generation in registered mode

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Sebastien Bourdeauducq 2011-12-13 14:08:39 +01:00
parent 0ea7a9b2e6
commit 92f24b784d
1 changed files with 1 additions and 1 deletions
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2
migen/bus/wishbone.py
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@ -113,7 +113,7 @@ class Decoder:
# combine cyc with slave selection signals # combine cyc with slave selection signals
i = 0 i = 0
for slave in self.slaves: for slave in self.slaves:
comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel_r[i])) comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel[i]))
i += 1 i += 1
# generate master ack (resp. err) by ORing all slave acks (resp. errs) # generate master ack (resp. err) by ORing all slave acks (resp. errs)