Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

wishbone: decoder: fix slave cyc generation in registered mode

This commit is contained in:
Sebastien Bourdeauducq 2011-12-13 14:08:39 +01:00
parent 0ea7a9b2e6
commit 92f24b784d
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
migen/bus/wishbone.py
View File

@ -113,7 +113,7 @@ class Decoder:
# combine cyc with slave selection signals
i = 0
for slave in self.slaves:
comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel_r[i]))
comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel[i]))
i += 1
# generate master ack (resp. err) by ORing all slave acks (resp. errs)