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targets: always use sys_clk_freq on SDRAM modules.

This commit is contained in:
Florent Kermarrec 2020-03-21 19:36:06 +01:00
parent ae6ef923af
commit 930679efd7
2 changed files with 2 additions and 2 deletions
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2
litex/boards/targets/de0nano.py
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@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16160(self.clk_freq, "1:1"), module = IS42S16160(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000), size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),

2
litex/boards/targets/genesys2.py
View File

@ -61,7 +61,7 @@ class BaseSoC(SoCCore):
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J256M16(self.clk_freq, "1:4"), module = MT41J256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000), size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),