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interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)

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This commit is contained in:
Florent Kermarrec 2020-02-26 15:13:16 +01:00
parent d324c54eee
commit 935e4effd2
1 changed files with 1 additions and 1 deletions
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2
litex/soc/interconnect/axi.py
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@ -56,7 +56,7 @@ def r_description(data_width, id_width):
]
class AXIInterface(Record):
def __init__(self, data_width, address_width, mode="master", id_width=1, clock_domain="sys"):
def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"):
self.data_width = data_width
self.address_width = address_width
self.id_width = id_width