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test/test_icap: Add IPROG sequence check.

This commit is contained in:
Florent Kermarrec 2021-10-04 14:41:38 +02:00
parent cb2f2d7021
commit 9416e30249
2 changed files with 28 additions and 6 deletions
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5
litex/soc/cores/icap.py
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@ -98,8 +98,9 @@ class ICAP(Module, AutoCSR):
self.comb += ps_send.i.eq(self.send) self.comb += ps_send.i.eq(self.send)
# Generate ICAP bitstream write sequence. # Generate ICAP bitstream write sequence.
self._csib = _csib = Signal(reset=1) self._csib = _csib = Signal(reset=1)
self._i = _i = Signal(32) self._rdwrb = _rdwrb = Signal()
self._i = _i = Signal(32)
self.sync.icap += [ self.sync.icap += [
_i.eq(ICAP_DUMMY), # Dummy (Default). _i.eq(ICAP_DUMMY), # Dummy (Default).
timeline(ps_send.o, [ timeline(ps_send.o, [

29
test/test_icap.py
View File

@ -10,24 +10,45 @@ from migen import *
from litex.soc.cores.icap import * from litex.soc.cores.icap import *
iprog_sequence = [
# csib rdwrb data
"0 0 0xaa995566",
"0 0 0x20000000",
"0 0 0x20000000",
"0 0 0x30008001",
"0 0 0x0000000f",
"0 0 0x20000000",
"0 0 0x20000000",
"0 0 0x30008001",
"0 0 0x0000000d",
"0 0 0x20000000",
"0 0 0x20000000",
]
class TestICAP(unittest.TestCase): class TestICAP(unittest.TestCase):
def test_icap_command_reload(self): def test_icap_command_reload(self):
def generator(dut): def generator(dut):
yield dut.addr.eq(ICAPRegisters.CMD) yield dut.addr.eq(ICAPRegisters.CMD)
yield dut.data.eq(ICAPCMDs.IPROG) yield dut.data.eq(ICAPCMDs.IPROG)
for i in range(16): for i in range(8):
yield yield
yield dut.send.eq(1) yield dut.send.eq(1)
yield yield
yield dut.send.eq(0) yield dut.send.eq(0)
for i in range(32):
print(f"{(yield dut._i):08x}") def check(dut):
while (yield dut._i) != ICAP_SYNC:
yield yield
for ref_w in iprog_sequence:
cur_w = f"{(yield dut._csib)} {(yield dut._rdwrb)} 0x{(yield dut._i):08x}"
self.assertEqual(ref_w, cur_w)
# print(cur_w)
yield
dut = ICAP(with_csr=False, simulation=True) dut = ICAP(with_csr=False, simulation=True)
clocks = {"sys": 10, "icap": 10} clocks = {"sys": 10, "icap": 10}
run_simulation(dut, generator(dut), clocks, vcd_name="icap.vcd") run_simulation(dut, [generator(dut), check(dut)], clocks, vcd_name="icap.vcd")
def test_icap_bitstream_syntax(self): def test_icap_bitstream_syntax(self):
dut = ICAPBitstream(simulation=True) dut = ICAPBitstream(simulation=True)