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soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone.

This commit is contained in:
Florent Kermarrec 2021-09-27 15:46:19 +02:00
parent ce0551b44a
commit 944732aa19
1 changed files with 2 additions and 4 deletions
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6
litex/soc/integration/soc.py
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@ -1333,12 +1333,10 @@ class LiteXSoC(SoC):
mem_wb = wishbone.Interface( mem_wb = wishbone.Interface(
data_width = self.cpu.mem_axi.data_width, data_width = self.cpu.mem_axi.data_width,
adr_width = 32-log2_int(self.cpu.mem_axi.data_width//8)) adr_width = 32-log2_int(self.cpu.mem_axi.data_width//8))
# FIXME: AXI2Wishbone FSMs must be reset with the CPU. mem_a2w = axi.AXI2Wishbone(
mem_a2w = ResetInserter()(axi.AXI2Wishbone(
axi = self.cpu.mem_axi, axi = self.cpu.mem_axi,
wishbone = mem_wb, wishbone = mem_wb,
base_address = 0)) base_address = 0)
self.comb += mem_a2w.reset.eq(ResetSignal() | self.cpu.reset)
self.submodules += mem_a2w self.submodules += mem_a2w
litedram_wb = wishbone.Interface(port.data_width) litedram_wb = wishbone.Interface(port.data_width)
self.submodules += LiteDRAMWishbone2Native( self.submodules += LiteDRAMWishbone2Native(