soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory.
- Replace im bus wishbone adaptation with synchronous memory (for now and initial tests). - Correctly handle dm bus wishbone adaptation (Added FIFO).
This commit is contained in:
Florent Kermarrec
parent
edb56e73aa
commit
9449d25911
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@ -10,6 +10,8 @@ from migen import *
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from litex.gen import *
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from litex.soc.interconnect import stream
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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@ -67,9 +69,9 @@ class uRV(CPU):
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# uRV Signals.
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# ------------
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im_addr = Signal(32)
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im_rd = Signal(1)
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im_rd = Signal()
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im_data = Signal(32)
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im_valid = Signal(1)
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im_valid = Signal()
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dm_addr = Signal(32)
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dm_data_s = Signal(32)
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@ -80,9 +82,6 @@ class uRV(CPU):
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dm_load_done = Signal()
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dm_store_done = Signal()
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rst_count = Signal(8, reset=16)
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self.sync += If(rst_count != 0, rst_count.eq(rst_count - 1))
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# uRV Instance.
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# -------------
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self.cpu_params = dict(
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@ -98,7 +97,7 @@ class uRV(CPU):
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# Clk / Rst.
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i_clk_i = ClockSignal("sys"),
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i_rst_i = ~(ResetSignal("sys") | self.reset | (rst_count != 0)),
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i_rst_i = ResetSignal("sys") | self.reset,
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# Instruction Mem Bus.
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o_im_addr_o = im_addr,
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@ -120,55 +119,92 @@ class uRV(CPU):
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# uRV Instruction Bus.
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# --------------------
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self.i_fsm = i_fsm = FSM(reset_state="IDLE")
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i_fsm.act("IDLE",
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If(im_rd,
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NextValue(im_valid, 0),
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NextState("READ")
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)
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)
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i_fsm.act("READ",
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ibus.stb.eq(1),
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ibus.cyc.eq(1),
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ibus.we.eq(0),
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ibus.adr.eq(im_addr),
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ibus.sel.eq(0b1111),
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If(ibus.ack,
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NextValue(im_valid, 1),
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NextValue(im_data, ibus.dat_r),
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NextState("IDLE")
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)
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from litex.soc.integration.common import get_mem_data
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try:
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# FIXME.
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rom_init = get_mem_data("build/sim/software/bios/bios.bin",
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data_width = 32,
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endianness = "little"
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)
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except:
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rom_init = []
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rom = Memory(32, depth=131072//4, init=rom_init)
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rom_port = rom.get_port()
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self.specials += rom, rom_port
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self.sync += im_valid.eq(1),
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self.comb += [
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rom_port.adr.eq(im_addr[2:]),
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im_data.eq(rom_port.dat_r),
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]
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# im_addr_d = Signal(32, reset=0xffffffff)
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# self.sync += im_addr_d.eq(im_addr)
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# self.i_fsm = i_fsm = FSM(reset_state="IDLE")
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# i_fsm.act("IDLE",
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# If(im_addr != im_addr_d,
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# NextValue(im_valid, 0),
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# NextState("READ")
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# )
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# )
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# i_fsm.act("READ",
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# ibus.stb.eq(1),
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# ibus.cyc.eq(1),
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# ibus.we.eq(0),
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# ibus.adr.eq(im_addr),
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# ibus.sel.eq(0b1111),
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# If(ibus.ack,
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# NextValue(im_valid, 1),
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# NextValue(im_data, ibus.dat_r),
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# NextState("IDLE")
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# )
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# )
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# uRV Data Bus.
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# -------------
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self.d_fsm = d_fsm = FSM(reset_state="IDLE")
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d_fsm.act("IDLE",
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If(dm_store,
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self.dm_fifo = dm_fifo = stream.SyncFIFO(
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layout = [("addr", 32), ("we", 1), ("data", 32), ("sel", 4)],
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depth = 16,
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)
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self.comb += [
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dm_fifo.sink.valid.eq(dm_store | dm_load),
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dm_fifo.sink.we.eq(dm_store),
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dm_fifo.sink.addr.eq(dm_addr),
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dm_fifo.sink.data.eq(dm_data_s),
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dm_fifo.sink.sel.eq(dm_data_select),
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]
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self.dm_fsm = dm_fsm = FSM(reset_state="IDLE")
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dm_fsm.act("IDLE",
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If(dm_fifo.source.valid,
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If(dm_fifo.source.we,
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NextState("WRITE")
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),
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If(dm_load,
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).Else(
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NextState("READ")
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)
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)
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d_fsm.act("WRITE",
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)
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dm_fsm.act("WRITE",
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dbus.stb.eq(1),
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dbus.cyc.eq(1),
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dbus.we.eq(1),
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dbus.adr.eq(dm_addr),
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dbus.sel.eq(dm_data_select),
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dbus.dat_w.eq(dm_data_s),
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dbus.adr.eq(dm_fifo.source.addr),
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dbus.sel.eq(dm_fifo.source.sel),
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dbus.dat_w.eq(dm_fifo.source.data),
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If(dbus.ack,
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dm_fifo.source.ready.eq(1),
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dm_store_done.eq(1),
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NextState("IDLE")
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)
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)
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d_fsm.act("READ",
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dm_fsm.act("READ",
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dbus.stb.eq(1),
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dbus.cyc.eq(1),
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dbus.we.eq(0),
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dbus.adr.eq(dm_addr),
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dbus.sel.eq(dm_data_select),
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dbus.adr.eq(dm_fifo.source.addr),
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dbus.sel.eq(dm_fifo.source.sel),
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If(dbus.ack,
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dm_fifo.source.ready.eq(1),
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dm_load_done.eq(1),
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dm_data_l.eq(dbus.dat_r),
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NextState("IDLE")
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