cores/cpu: revert vexriscv (it seems there is a regression in last version)

2018-10-02 12:20:32 +02:00 · 2018-10-02 12:20:32 +02:00 · 948527b0fe
parent 15bca4535f
commit 948527b0fe
2 changed files with 3 additions and 3 deletions
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@ -1 +1 @@
-Subproject commit e8a30b95b9aa1445b5a4a76579a98a0552e2db53
+Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5
--- a/litex/soc/software/include/base/csr-defs.h
+++ b/litex/soc/software/include/base/csr-defs.h
@ -3,8 +3,8 @@

 #define CSR_MSTATUS_MIE 0x8

-#define CSR_IRQ_MASK 0xBC0
-#define CSR_IRQ_PENDING 0xFC0
+#define CSR_IRQ_MASK 0x330
+#define CSR_IRQ_PENDING 0x360

 #define CSR_DCACHE_INFO 0xCC0