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boards/platforms/versa_ecp5: fix mising update.

This commit is contained in:
Florent Kermarrec 2020-07-01 08:35:54 +02:00
parent c0dba18d59
commit 949a8e73c2
1 changed files with 3 additions and 2 deletions
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5
litex/boards/platforms/versa_ecp5.py
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@ -221,8 +221,9 @@ class Platform(LatticePlatform):
default_clk_name = "clk100" default_clk_name = "clk100"
default_clk_period = 1e9/100e6 default_clk_period = 1e9/100e6
def __init__(self, **kwargs): def __init__(self, device="LFE5UM5G", **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs) assert device in ["LFE5UM5G", "LFE5UM"]
LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, **kwargs)
def create_programmer(self): def create_programmer(self):
return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg") return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")