Merge pull request #400 from Xiretza/ecp5-pll-freqfix

Fix ECP5PLL VCO frequency range
2020-02-24 14:49:35 +01:00 · 2020-02-24 14:49:35 +01:00 · 9521f2ff80
parent 0c7e0bf025 7a87d4e262
commit 9521f2ff80
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@ -507,7 +507,7 @@ class ECP5PLL(Module):
    clko_div_range  = (1, 128+1)
    clki_freq_range = (    8e6,  400e6)
    clko_freq_range = (3.125e6,  400e6)
-    vco_freq_range  = (  550e6, 1250e6)
+    vco_freq_range  = (  400e6,  800e6)

    def __init__(self):
        self.reset      = Signal()