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reorganize core files

This commit is contained in:
Florent Kermarrec 2015-02-04 19:57:20 +01:00
parent 97daf9bd85
commit 957c16264a
9 changed files with 16 additions and 16 deletions
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12
liteeth/__init__.py
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@ -1,12 +0,0 @@
from liteeth.common import *
from liteeth.mac import LiteEthMAC
from liteeth.arp import LiteEthARP
from liteeth.ip import LiteEthIP
class LiteEthIPStack(Module, AutoCSR):
def __init__(self, phy, mac_address, ip_address):
self.phy = phy
self.submodules.mac = mac = LiteEthMAC(phy, 8, interface="crossbar", with_hw_preamble_crc=True)
self.submodules.arp = arp = LiteEthARP(mac, mac_address, ip_address)
self.submodules.ip = ip = LiteEthIP(mac, mac_address, ip_address, arp.table)
self.sink, self.source = self.ip.sink, self.ip.source

12
liteeth/core/__init__.py Normal file
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@ -0,0 +1,12 @@
from liteeth.common import *
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
class LiteEthIPCore(Module, AutoCSR):
def __init__(self, phy, mac_address, ip_address):
self.phy = phy
self.submodules.mac = mac = LiteEthMAC(phy, 8, interface="crossbar", with_hw_preamble_crc=True)
self.submodules.arp = arp = LiteEthARP(mac, mac_address, ip_address)
self.submodules.ip = ip = LiteEthIP(mac, mac_address, ip_address, arp.table)
self.sink, self.source = self.ip.sink, self.ip.source

0
liteeth/arp/__init__.py → liteeth/core/arp.py
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0
liteeth/ip/__init__.py → liteeth/core/ip.py
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0
liteeth/udp/__init__.py → liteeth/core/udp.py
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0
liteeth/frontend/__init__.py Normal file
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0
liteeth/etherbone/__init__.py → liteeth/frontend/etherbone.py
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4
liteeth/test/arp_tb.py
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@ -5,7 +5,7 @@ from migen.sim.generic import run_simulation
from liteeth.common import *
from liteeth.mac import LiteEthMAC
from liteeth.arp import LiteEthARP
from liteeth.core.arp import LiteEthARP
from liteeth.test.common import *
from liteeth.test.model import phy, mac, arp
@ -15,7 +15,7 @@ mac_address = 0x12345678abcd
class TB(Module):
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=True)
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)

4
liteeth/test/ip_tb.py
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@ -4,7 +4,7 @@ from migen.bus.transactions import *
from migen.sim.generic import run_simulation
from liteeth.common import *
from liteeth import LiteEthIPStack
from liteeth.core import LiteEthIPCore
from liteeth.test.common import *
from liteeth.test.model import phy, mac, arp, ip
@ -19,7 +19,7 @@ class TB(Module):
self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=True)
self.submodules.ip = LiteEthIPStack(self.phy_model, mac_address, ip_address)
self.submodules.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address)
# use sys_clk for each clock_domain
self.clock_domains.cd_eth_rx = ClockDomain()