bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).

litex/boards/targets/kcu105.py

@@ -68,7 +68,6 @@ class BaseSoC(SoCCore):
                 iodelay_clk_freq = 200e6,
                 cmd_latency      = 1)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = EDY4016A(sys_clk_freq, "1:4"),

litex/soc/software/bios/Makefile

@@ -11,12 +11,12 @@ CFLAGS += -DTFTP_SERVER_PORT=$(TFTP_SERVER_PORT)
 endif
 
 OBJECTS = isr.o			\
-	  sdram.o		\
+	  sdram.o			\
-	  sdcard.o		\
+	  sdcard.o			\
-	  main.o		\
+	  main.o			\
 	  boot-helper.o		\
-	  boot.o		\
+	  boot.o			\
-	  helpers.o		\
+	  helpers.o			\
 	  cmd_bios.o		\
 	  cmd_boot.o		\
 	  cmd_dram.o		\
@@ -24,7 +24,6 @@ OBJECTS = isr.o			\
 	  cmd_mem_access.o	\
 	  cmd_sdcard.o		\
 	  cmd_spi_flash.o	\
-	  cmd_usddrphy.o
 
 ifneq "$(or $(TERM_NO_COMPLETE),$(TERM_MINI))" ""
 CFLAGS += -DTERM_NO_COMPLETE

litex/soc/software/bios/commands/cmd_usddrphy.c

@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: BSD-Source-Code
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <generated/csr.h>
-
-#include "../command.h"
-#include "../helpers.h"
-#include "../sdram.h"
-
-/**
- * Command "sdram_cdly"
- *
- * Set SDRAM clk/cmd delay
- *
- */
-#ifdef USDDRPHY_DEBUG
-static void sdram_cdly(int nb_params, char **params)
-{
-	unsigned int delay;
-	char *c;
-
-	if (nb_params < 1) {
-		printf("sdram_cdly <delay>");
-		return;
-	}
-
-	delay = strtoul(params[0], &c, 0);
-	if (*c != 0) {
-		printf("Incorrect delay");
-		return;
-	}
-
-	ddrphy_cdly(delay);
-}
-
-define_command(sdram_cdly, sdram_cdly, "Set SDRAM clk/cmd delay", DDR_CMDS);
-#endif
-
-/**
- * Command "sdram_cdly"
- *
- * Run SDRAM calibration
- *
- */
-#ifdef USDDRPHY_DEBUG
-define_command(sdram_cal, sdram_cal, "Run SDRAM calibration", DDR_CMDS);
-#endif
-
-/**
- * Command "sdram_mpr"
- *
- * Read SDRAM MPR
- *
- */
-#ifdef USDDRPHY_DEBUG
-define_command(sdram_mpr, sdram_mpr, "Read SDRAM MPR", DDR_CMDS);
-#endif
-
-
-/**
- * Command "sdram_mrwr"
- *
- * Write SDRAM mode registers
- *
- */
-#ifdef USDDRPHY_DEBUG
-static void sdram_mrwr(int nb_params, char **params)
-{
-	unsigned int reg;
-	unsigned int value;
-	char *c;
-
-	if (nb_params < 2) {
-		printf("sdram_mrwr <reg> <value>");
-		return;
-	}
-
-	reg = strtoul(params[0], &c, 0);
-	if (*c != 0) {
-		printf("Incorrect register value");
-		return;
-	}
-
-	value = strtoul(params[1], &c, 0);
-	if (*c != 0) {
-		printf("Incorrect value");
-		return;
-	}
-
-	sdrsw();
-	printf("Writing 0x%04x to SDRAM mode register %d\n", value, reg);
-	sdrmrwr(reg, value);
-	sdrhw();
-}
-
-define_command(sdram_mrwr, sdram_mrwr, "Write SDRAM mode registers", DDR_CMDS);
-#endif
-
-/**
- * Command "sdram_cdly_scan"
- *
- * Enable/disable cdly scan
- *
- */
-#ifdef USDDRPHY_DEBUG
-static void sdram_cdly_scan(int nb_params, char **params)
-{
-	unsigned int value;
-	char *c;
-
-	if (nb_params < 1) {
-		printf("sdram_cdly_scan <value>");
-		return;
-	}
-
-	value = strtoul(params[0], &c, 0);
-	if (*c != 0) {
-		printf("Incorrect value");
-		return;
-	}
-
-	sdr_cdly_scan(value);
-}
-
-define_command(sdram_cdly_scan, sdram_cdly_scan, "Enable/disable cdly scan", DDR_CMDS);
-#endif

litex/soc/software/bios/sdram.c

@@ -166,7 +166,7 @@ void sdrwr(unsigned int addr)
 
 #ifdef CSR_DDRPHY_BASE
 
-#if defined(DDRPHY_CMD_DELAY) || defined(USDDRPHY_DEBUG)
+#if defined(DDRPHY_CMD_DELAY)
 void ddrphy_cdly(unsigned int delay) {
 	printf("Setting clk/cmd delay to %d taps\n", delay);
 #if CSR_DDRPHY_EN_VTC_ADDR
@@ -1048,93 +1048,4 @@ int sdrinit(void)
 	return 1;
 }
 
-#ifdef USDDRPHY_DEBUG
-
-#define MPR0_SEL (0 << 0)
-#define MPR1_SEL (1 << 0)
-#define MPR2_SEL (2 << 0)
-#define MPR3_SEL (3 << 0)
-
-#define MPR_ENABLE (1 << 2)
-
-#define MPR_READ_SERIAL    (0 << 11)
-#define MPR_READ_PARALLEL  (1 << 11)
-#define MPR_READ_STAGGERED (2 << 11)
-
-void sdrcal(void)
-{
-#ifdef CSR_DDRPHY_BASE
-#if CSR_DDRPHY_EN_VTC_ADDR
-	ddrphy_en_vtc_write(0);
-#endif
-	sdrlevel();
-#if CSR_DDRPHY_EN_VTC_ADDR
-	ddrphy_en_vtc_write(1);
-#endif
-#endif
-	sdrhw();
-}
-
-void sdrmrwr(char reg, int value) {
-	sdram_dfii_pi0_address_write(value);
-	sdram_dfii_pi0_baddress_write(reg);
-	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
-}
-
-static void sdrmpron(char mpr)
-{
-	sdrmrwr(3, MPR_READ_SERIAL | MPR_ENABLE | mpr);
-}
-
-static void sdrmproff(void)
-{
-	sdrmrwr(3, 0);
-}
-
-void sdrmpr(void)
-{
-	int module, phase;
-	unsigned char buf[DFII_PIX_DATA_BYTES];
-	printf("Read SDRAM MPR...\n");
-
-	/* rst phy */
-	for(module=0; module<SDRAM_PHY_MODULES; module++) {
-#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
-		write_delay_rst(module);
-#endif
-		read_delay_rst(module);
-		read_bitslip_rst(module);
-	}
-
-	/* software control */
-	sdrsw();
-
-	printf("Reads with MPR0 (0b01010101) enabled...\n");
-	sdrmpron(MPR0_SEL);
-	command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
-	cdelay(15);
-	for (module=0; module < SDRAM_PHY_MODULES; module++) {
-		printf("m%d: ", module);
-		for(phase=0; phase<SDRAM_PHY_PHASES; phase++) {
-			csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr[phase],
-					 buf, DFII_PIX_DATA_BYTES);
-			printf("%d", buf[  SDRAM_PHY_MODULES-module-1] & 0x1);
-			printf("%d", buf[2*SDRAM_PHY_MODULES-module-1] & 0x1);
-		}
-		printf("\n");
-	}
-	sdrmproff();
-
-	/* hardware control */
-	sdrhw();
-}
-
-void sdr_cdly_scan(int enabled)
-{
-	printf("Turning cdly scan %s\n", enabled ? "ON" : "OFF");
-	_write_level_cdly_scan = enabled;
-}
-
-#endif
-
 #endif

litex/soc/software/bios/sdram.h

@@ -25,11 +25,4 @@ int sdrinit(void);
 void ddrphy_cdly(unsigned int delay);
 #endif
 
-#ifdef USDDRPHY_DEBUG
-void sdrcal(void);
-void sdrmrwr(char reg, int value);
-void sdrmpr(void);
-void sdr_cdly_scan(int enabled);
-#endif
-
 #endif /* __SDRAM_H */