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cores/video: Mode VideoVGAPHY/VideoDVIPHY and add separators.

This commit is contained in:
Florent Kermarrec 2021-03-05 14:25:41 +01:00
parent 0280a9dd57
commit 9624cce188
1 changed files with 27 additions and 22 deletions
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49
litex/soc/cores/video.py
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@ -618,6 +618,33 @@ class VideoFrameBuffer(Module, AutoCSR):
# Video PHYs --------------------------------------------------------------------------------------- # Video PHYs ---------------------------------------------------------------------------------------
class Open(Signal): pass
# VGA (Generic).
class VideoVGAPHY(Module):
def __init__(self, pads, clock_domain="sys"):
self.sink = sink = stream.Endpoint(video_data_layout)
# # #
# Always ack Sink, no backpressure.
self.comb += sink.ready.eq(1)
# Drive VGA Conrols.
self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))
# Drive VGA Datas.
cbits = len(pads.r)
cshift = (8 - cbits)
for i in range(cbits):
self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
# DVI (Generic).
class VideoDVIPHY(Module): class VideoDVIPHY(Module):
def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True): def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True):
self.sink = sink = stream.Endpoint(video_data_layout) self.sink = sink = stream.Endpoint(video_data_layout)
@ -645,25 +672,3 @@ class VideoDVIPHY(Module):
self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
class VideoVGAPHY(Module):
def __init__(self, pads, clock_domain="sys"):
self.sink = sink = stream.Endpoint(video_data_layout)
# # #
# Always ack Sink, no backpressure.
self.comb += sink.ready.eq(1)
# Drive VGA Conrols.
self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))
# Drive VGA Datas.
cbits = len(pads.r)
cshift = (8 - cbits)
for i in range(cbits):
self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))