Got litex dma to work with vexii

2024-04-08 16:45:15 +02:00 · 2024-04-08 16:45:15 +02:00 · 9654b40864
parent 8f86108eed
commit 9654b40864
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/vexiiriscv/core.py
+++ b/litex/soc/cores/cpu/vexiiriscv/core.py
@ -217,7 +217,7 @@ class VexiiRiscv(CPU):
        )

        if VexiiRiscv.with_dma:
-            self.dma_bus = dma_bus = axi.AXIInterface(data_width=VexiiRiscv.perf_bus_width, address_width=32, id_width=4)
+            self.dma_bus = dma_bus = axi.AXIInterface(data_width=VexiiRiscv.internal_bus_width, address_width=32, id_width=4)

            self.cpu_params.update(
                # DMA Bus.