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Got litex dma to work with vexii

This commit is contained in:
Dolu1990 2024-04-08 16:45:15 +02:00
parent 8f86108eed
commit 9654b40864
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/cpu/vexiiriscv/core.py
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@ -217,7 +217,7 @@ class VexiiRiscv(CPU):
) )
if VexiiRiscv.with_dma: if VexiiRiscv.with_dma:
self.dma_bus = dma_bus = axi.AXIInterface(data_width=VexiiRiscv.perf_bus_width, address_width=32, id_width=4) self.dma_bus = dma_bus = axi.AXIInterface(data_width=VexiiRiscv.internal_bus_width, address_width=32, id_width=4)
self.cpu_params.update( self.cpu_params.update(
# DMA Bus. # DMA Bus.