VexRiscv-SMP: Review/Cleanup #906.
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@ -109,9 +109,9 @@ class VexRiscvSMP(CPU):
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if(args.cpu_per_fpu):
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VexRiscvSMP.cpu_per_fpu = args.cpu_per_fpu
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if(args.with_rvc):
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VexRiscvSMP.with_rvc = True
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if(args.dtlb_size): VexRiscvSMP.dtlb_size = int(args.dtlb_size)
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if(args.itlb_size): VexRiscvSMP.itlb_size = int(args.itlb_size)
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VexRiscvSMP.with_rvc = True
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if(args.dtlb_size): VexRiscvSMP.dtlb_size = int(args.dtlb_size)
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if(args.itlb_size): VexRiscvSMP.itlb_size = int(args.itlb_size)
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# ABI.
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@staticmethod
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@ -372,7 +372,7 @@ class VexRiscvSMP(CPU):
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# Define number of CPUs
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soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
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soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())
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# constants for cache so we can add them in the DTS
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# Constants for cache so we can add them in the DTS.
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if (VexRiscvSMP.dcache_size > 0):
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soc.add_constant("cpu_dcache_size", VexRiscvSMP.dcache_size)
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soc.add_constant("cpu_dcache_ways", VexRiscvSMP.dcache_ways)
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@ -381,8 +381,8 @@ class VexRiscvSMP(CPU):
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soc.add_constant("cpu_icache_size", VexRiscvSMP.icache_size)
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soc.add_constant("cpu_icache_ways", VexRiscvSMP.icache_ways)
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soc.add_constant("cpu_icache_block_size", 64) # hardwired?
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# constants for TLB so we can add them in the DTS
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# full associative so only the size is described
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# Constants for TLB so we can add them in the DTS
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# full associative so only the size is described.
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if (VexRiscvSMP.dtlb_size > 0):
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soc.add_constant("cpu_dtlb_size", VexRiscvSMP.dtlb_size)
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soc.add_constant("cpu_dtlb_ways", VexRiscvSMP.dtlb_size)
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@ -60,38 +60,50 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
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# CPU ------------------------------------------------------------------------------------------
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# VexRiscv-SMP
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# ------------
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if cpu_name == "vexriscv smp-linux":
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# cache description
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# Cache description.
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cache_desc = ""
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if "cpu_dcache_size" in d["constants"]:
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cache_desc += """
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d-cache-size = <{d_cache_size}>;
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d-cache-sets = <{d_cache_ways}>;
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d-cache-block-size = <{d_cache_block_size}>;
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""".format(d_cache_size=d["constants"]["cpu_dcache_size"], d_cache_ways=d["constants"]["cpu_dcache_ways"], d_cache_block_size=d["constants"]["cpu_dcache_block_size"])
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""".format(
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d_cache_size = d["constants"]["cpu_dcache_size"],
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d_cache_ways = d["constants"]["cpu_dcache_ways"],
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d_cache_block_size = d["constants"]["cpu_dcache_block_size"])
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if "cpu_icache_size" in d["constants"]:
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cache_desc += """
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i-cache-size = <{i_cache_size}>;
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i-cache-sets = <{i_cache_ways}>;
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i-cache-block-size = <{i_cache_block_size}>;
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""".format(i_cache_size=d["constants"]["cpu_icache_size"], i_cache_ways=d["constants"]["cpu_icache_ways"], i_cache_block_size=d["constants"]["cpu_icache_block_size"])
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""".format(
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i_cache_size = d["constants"]["cpu_icache_size"],
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i_cache_ways = d["constants"]["cpu_icache_ways"],
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i_cache_block_size = d["constants"]["cpu_icache_block_size"])
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# tlb description
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# TLB description.
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tlb_desc = ""
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if "cpu_dtlb_size" in d["constants"]:
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tlb_desc += """
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d-tlb-size = <{d_tlb_size}>;
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d-tlb-sets = <{d_tlb_ways}>;
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""".format(d_tlb_size=d["constants"]["cpu_dtlb_size"], d_tlb_ways=d["constants"]["cpu_dtlb_ways"])
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""".format(
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d_tlb_size = d["constants"]["cpu_dtlb_size"],
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d_tlb_ways = d["constants"]["cpu_dtlb_ways"])
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if "cpu_itlb_size" in d["constants"]:
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tlb_desc += """
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i-tlb-size = <{i_tlb_size}>;
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i-tlb-sets = <{i_tlb_ways}>;
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""".format(i_tlb_size=d["constants"]["cpu_itlb_size"], i_tlb_ways=d["constants"]["cpu_itlb_ways"])
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""".format(
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i_tlb_size = d["constants"]["cpu_itlb_size"],
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i_tlb_ways = d["constants"]["cpu_itlb_ways"])
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# CPU(s) Count.
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cpus = range(int(d["constants"]["config_cpu_count"]))
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# topology
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# CPU(s) Topology.
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cpu_map = ""
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if int(d["constants"]["config_cpu_count"]) > 1:
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cpu_map += """
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@ -136,7 +148,8 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
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}};
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""".format(cpu_map=cpu_map)
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# mor1kx
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# Mor1kx
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# ------
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elif cpu_name == "mor1kx":
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dts += """
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cpus {{
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