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VexRiscv-SMP: Review/Cleanup #906.

This commit is contained in:
Florent Kermarrec 2021-06-18 10:19:27 +02:00
parent 58c533668c
commit 98676162a3
2 changed files with 27 additions and 14 deletions
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6
litex/soc/cores/cpu/vexriscv_smp/core.py
View File

@ -372,7 +372,7 @@ class VexRiscvSMP(CPU):
# Define number of CPUs
soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())
# constants for cache so we can add them in the DTS
# Constants for cache so we can add them in the DTS.
if (VexRiscvSMP.dcache_size > 0):
soc.add_constant("cpu_dcache_size", VexRiscvSMP.dcache_size)
soc.add_constant("cpu_dcache_ways", VexRiscvSMP.dcache_ways)
@ -381,8 +381,8 @@ class VexRiscvSMP(CPU):
soc.add_constant("cpu_icache_size", VexRiscvSMP.icache_size)
soc.add_constant("cpu_icache_ways", VexRiscvSMP.icache_ways)
soc.add_constant("cpu_icache_block_size", 64) # hardwired?
# constants for TLB so we can add them in the DTS
# full associative so only the size is described
# Constants for TLB so we can add them in the DTS
# full associative so only the size is described.
if (VexRiscvSMP.dtlb_size > 0):
soc.add_constant("cpu_dtlb_size", VexRiscvSMP.dtlb_size)
soc.add_constant("cpu_dtlb_ways", VexRiscvSMP.dtlb_size)

29
litex/tools/litex_json2dts.py
View File

@ -60,38 +60,50 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
# CPU ------------------------------------------------------------------------------------------
# VexRiscv-SMP
# ------------
if cpu_name == "vexriscv smp-linux":
# cache description
# Cache description.
cache_desc = ""
if "cpu_dcache_size" in d["constants"]:
cache_desc += """
d-cache-size = <{d_cache_size}>;
d-cache-sets = <{d_cache_ways}>;
d-cache-block-size = <{d_cache_block_size}>;
""".format(d_cache_size=d["constants"]["cpu_dcache_size"], d_cache_ways=d["constants"]["cpu_dcache_ways"], d_cache_block_size=d["constants"]["cpu_dcache_block_size"])
""".format(
d_cache_size = d["constants"]["cpu_dcache_size"],
d_cache_ways = d["constants"]["cpu_dcache_ways"],
d_cache_block_size = d["constants"]["cpu_dcache_block_size"])
if "cpu_icache_size" in d["constants"]:
cache_desc += """
i-cache-size = <{i_cache_size}>;
i-cache-sets = <{i_cache_ways}>;
i-cache-block-size = <{i_cache_block_size}>;
""".format(i_cache_size=d["constants"]["cpu_icache_size"], i_cache_ways=d["constants"]["cpu_icache_ways"], i_cache_block_size=d["constants"]["cpu_icache_block_size"])
""".format(
i_cache_size = d["constants"]["cpu_icache_size"],
i_cache_ways = d["constants"]["cpu_icache_ways"],
i_cache_block_size = d["constants"]["cpu_icache_block_size"])
# tlb description
# TLB description.
tlb_desc = ""
if "cpu_dtlb_size" in d["constants"]:
tlb_desc += """
d-tlb-size = <{d_tlb_size}>;
d-tlb-sets = <{d_tlb_ways}>;
""".format(d_tlb_size=d["constants"]["cpu_dtlb_size"], d_tlb_ways=d["constants"]["cpu_dtlb_ways"])
""".format(
d_tlb_size = d["constants"]["cpu_dtlb_size"],
d_tlb_ways = d["constants"]["cpu_dtlb_ways"])
if "cpu_itlb_size" in d["constants"]:
tlb_desc += """
i-tlb-size = <{i_tlb_size}>;
i-tlb-sets = <{i_tlb_ways}>;
""".format(i_tlb_size=d["constants"]["cpu_itlb_size"], i_tlb_ways=d["constants"]["cpu_itlb_ways"])
""".format(
i_tlb_size = d["constants"]["cpu_itlb_size"],
i_tlb_ways = d["constants"]["cpu_itlb_ways"])
# CPU(s) Count.
cpus = range(int(d["constants"]["config_cpu_count"]))
# topology
# CPU(s) Topology.
cpu_map = ""
if int(d["constants"]["config_cpu_count"]) > 1:
cpu_map += """
@ -136,7 +148,8 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
}};
""".format(cpu_map=cpu_map)
# mor1kx
# Mor1kx
# ------
elif cpu_name == "mor1kx":
dts += """
cpus {{