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tools/litex_sim: also add CPU's dbus to analyzer_signals (to demonstrate triggers in wiki).

This commit is contained in:
Florent Kermarrec 2020-11-06 12:49:43 +01:00
parent 61c009a393
commit 996be95725
1 changed files with 10 additions and 0 deletions
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10
litex/tools/litex_sim.py
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@ -281,6 +281,7 @@ class SimSoC(SoCCore):
# Analyzer --------------------------------------------------------------------------------- # Analyzer ---------------------------------------------------------------------------------
if with_analyzer: if with_analyzer:
analyzer_signals = [ analyzer_signals = [
# IBus (could also just added as self.cpu.ibus)
self.cpu.ibus.stb, self.cpu.ibus.stb,
self.cpu.ibus.cyc, self.cpu.ibus.cyc,
self.cpu.ibus.adr, self.cpu.ibus.adr,
@ -289,6 +290,15 @@ class SimSoC(SoCCore):
self.cpu.ibus.sel, self.cpu.ibus.sel,
self.cpu.ibus.dat_w, self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r, self.cpu.ibus.dat_r,
# DBus (could also just added as self.cpu.dbus)
self.cpu.dbus.stb,
self.cpu.dbus.cyc,
self.cpu.dbus.adr,
self.cpu.dbus.we,
self.cpu.dbus.ack,
self.cpu.dbus.sel,
self.cpu.dbus.dat_w,
self.cpu.dbus.dat_r,
] ]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512, depth = 512,