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clean up

This commit is contained in:
Florent Kermarrec 2013-03-22 13:50:16 +01:00
parent 5e48f9c005
commit 99a78b8e33
3 changed files with 5 additions and 7 deletions
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2
examples/de0_nano/client/test_mila.py
View File

@ -31,8 +31,6 @@ mila = mila.MiLa(MILA_ADDR, trigger, recorder, csr)
dat_vcd = VcdDat(dat_w) dat_vcd = VcdDat(dat_w)
def capture(size): def capture(size):
global trigger
global recorder
global dat_vcd global dat_vcd
sum_tt = gen_truth_table("term") sum_tt = gen_truth_table("term")
mila.trigger.sum.set(sum_tt) mila.trigger.sum.set(sum_tt)

8
miscope/bridges/spi2csr/__init__.py
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@ -4,13 +4,13 @@ from migen.genlib.cdc import *
from migen.bus import csr from migen.bus import csr
class Spi2Csr(Module): class Spi2Csr(Module):
def __init__(self, a_w, d_w, burst_length=8): def __init__(self, burst_length=8):
self.a_w = a_w self.a_w = 14
self.d_w = d_w self.d_w = 8
self.burst_length = 8 self.burst_length = 8
# Csr interface # Csr interface
self.csr = csr.Interface(self.a_w, self.d_w) self.csr = csr.Interface()
# Spi interface # Spi interface
self.spi_clk = Signal() self.spi_clk = Signal()

2
miscope/bridges/uart2csr/__init__.py
View File

@ -16,7 +16,7 @@ class Uart2Csr(Module):
self.tx = Signal() self.tx = Signal()
# Csr interface # Csr interface
self.csr = csr.Interface(32, 8) self.csr = csr.Interface()
### ###