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soc/integration/soc_sdram: allow using axi interface with litedram

This commit is contained in:
Florent Kermarrec 2018-11-09 15:42:34 +01:00
parent 416bdb6483
commit 9a6447172a
1 changed files with 12 additions and 3 deletions
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15
litex/soc/integration/soc_sdram.py
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@ -5,7 +5,8 @@ from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR from litex.soc.interconnect.csr import AutoCSR
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litedram.frontend.wishbone import LiteDRAMWishbone2Native from litedram.frontend.wishbone import *
from litedram.frontend.axi import *
from litedram import dfii, core from litedram import dfii, core
@ -51,7 +52,7 @@ class SoCSDRAM(SoCCore):
raise FinalizeError raise FinalizeError
self._wb_sdram_ifs.append(interface) self._wb_sdram_ifs.append(interface)
def register_sdram(self, phy, geom_settings, timing_settings, **kwargs): def register_sdram(self, phy, geom_settings, timing_settings, use_axi=False, **kwargs):
assert not self._sdram_phy assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
@ -84,7 +85,15 @@ class SoCSDRAM(SoCCore):
self.submodules.l2_cache = FullMemoryWE()(l2_cache) self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else: else:
self.submodules.l2_cache = l2_cache self.submodules.l2_cache = l2_cache
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port) if use_axi:
axi_port = LiteDRAMAXIPort(
port.data_width,
port.address_width + log2_int(port.data_width//8))
axi2native = LiteDRAMAXI2Native(axi_port, port)
self.submodules += axi2native
self.submodules.wishbone_bridge = LiteDRAMWishbone2AXI(self.l2_cache.slave, axi_port)
else:
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
def do_finalize(self): def do_finalize(self):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size: