cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore)
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@ -88,13 +88,10 @@ class RocketRV64(CPU):
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self.mem_axi = mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
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self.mem_axi = mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
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self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
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self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
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self.mem_wb64 = mem_wb64 = wishbone.Interface(data_width=64, adr_width=29)
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self.mem_wb = mem_wb = wishbone.Interface(data_width=64, adr_width=29)
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self.mmio_wb64 = mmio_wb64 = wishbone.Interface(data_width=64, adr_width=29)
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self.mmio_wb = mmio_wb = wishbone.Interface(data_width=64, adr_width=29)
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self.mem_wb32 = mem_wb32 = wishbone.Interface()
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self.buses = [mem_wb, mmio_wb]
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self.mmio_wb32 = mmio_wb32 = wishbone.Interface()
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self.buses = [mem_wb32, mmio_wb32]
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# # #
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# # #
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@ -210,19 +207,14 @@ class RocketRV64(CPU):
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)
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)
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# adapt axi interfaces to wishbone
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# adapt axi interfaces to wishbone
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mem_a2w = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb64, base_address=0))
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mem_a2w = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb, base_address=0))
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mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb64, base_address=0))
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mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
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# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
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# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
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self.comb += [
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self.comb += [
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mem_a2w.reset.eq( ResetSignal() | self.reset),
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mem_a2w.reset.eq( ResetSignal() | self.reset),
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mmio_a2w.reset.eq(ResetSignal() | self.reset),
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mmio_a2w.reset.eq(ResetSignal() | self.reset),
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]
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]
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self.submodules += mem_a2w, mmio_a2w
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# down-convert wishbone from 64 to 32 bit data width
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mem_dc = wishbone.Converter(mem_wb64, mem_wb32)
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mmio_dc = wishbone.Converter(mmio_wb64, mmio_wb32)
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self.submodules += mem_a2w, mem_dc, mmio_a2w, mmio_dc
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# add verilog sources
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# add verilog sources
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self.add_sources(platform, variant)
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self.add_sources(platform, variant)
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