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transport_tb: add basic test for TX path

This commit is contained in:
Florent Kermarrec 2014-12-12 11:22:21 +01:00
parent 7ea46ed7a6
commit 9ae703efbe
3 changed files with 35 additions and 9 deletions
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2
lib/sata/test/Makefile
View File

@ -20,7 +20,7 @@ link_tb:
transport_tb: transport_tb:
$(CMD) transport_tb.py $(CMD) transport_tb.py
all: crc_tb scrambler_tb all: crc_tb scrambler_tb link_tb
clean: clean:
rm crc scrambler *.vcd rm crc scrambler *.vcd

4
lib/sata/test/bfm.py
View File

@ -327,6 +327,8 @@ class FIS_DATA(FIS):
def __repr__(self): def __repr__(self):
r = "FIS_DATA\n" r = "FIS_DATA\n"
r += FIS.__repr__(self) r += FIS.__repr__(self)
for data in self.packet[1:]:
r += "%08x\n" %data
return r return r
class FIS_PIO_SETUP_D2H(FIS): class FIS_PIO_SETUP_D2H(FIS):
@ -365,7 +367,7 @@ class TransportLayer(Module):
elif fis_type == fis_types["DMA_ACTIVATE_D2H"]: elif fis_type == fis_types["DMA_ACTIVATE_D2H"]:
fis = FIS_DMA_ACTIVATE_D2H(packet) fis = FIS_DMA_ACTIVATE_D2H(packet)
elif fis_type == fis_types["DMA_SETUP"]: elif fis_type == fis_types["DMA_SETUP"]:
fis = FIS_SETUP(packet) fis = FIS_DMA_SETUP(packet)
elif fis_type == fis_types["DATA"]: elif fis_type == fis_types["DATA"]:
fis = FIS_DATA(packet) fis = FIS_DATA(packet)
elif fis_type == fis_types["PIO_SETUP_D2H"]: elif fis_type == fis_types["PIO_SETUP_D2H"]:

38
lib/sata/test/transport_tb.py
View File

@ -14,15 +14,39 @@ from lib.sata.test.common import *
class TB(Module): class TB(Module):
def __init__(self): def __init__(self):
self.submodules.bfm = BFM(phy_debug=False, self.submodules.bfm = BFM(phy_debug=False,
link_random_level=50, transport_debug=True, transport_loopback=True) link_random_level=0, transport_debug=True, transport_loopback=True)
self.submodules.link = SATALinkLayer(self.bfm.phy) self.submodules.link = SATALinkLayer(self.bfm.phy)
self.submodules.transport = SATATransportLayer(self.link) self.submodules.transport = SATATransportLayer(self.link)
self.comb += [ def gen_simulation(self, selfp):
self.transport.tx.cmd.stb.eq(1), for i in range(100):
self.transport.tx.cmd.type.eq(fis_types["REG_H2D"]), yield
self.transport.tx.cmd.lba.eq(0x12345678) selfp.transport.tx.cmd.stb = 1
] selfp.transport.tx.cmd.type = fis_types["REG_H2D"]
selfp.transport.tx.cmd.lba = 0x0123456789
yield
while selfp.transport.tx.cmd.ack == 0:
yield
selfp.transport.tx.cmd.stb = 1
selfp.transport.tx.cmd.type = fis_types["DMA_SETUP"]
selfp.transport.tx.cmd.dma_buffer_id = 0x0123456789ABCDEF
yield
while selfp.transport.tx.cmd.ack == 0:
yield
selfp.transport.tx.cmd.stb = 1
selfp.transport.tx.cmd.type = fis_types["DATA"]
yield
for i in range(32):
selfp.transport.tx.data.stb = 1
#selfp.transport.tx.data.sop = (i==0)
selfp.transport.tx.data.eop = (i==31)
selfp.transport.tx.data.d = i
if selfp.transport.tx.data.ack == 1:
yield
else:
while selfp.transport.tx.data.ack == 0:
yield
selfp.transport.tx.cmd.stb = 0
if __name__ == "__main__": if __name__ == "__main__":
run_simulation(TB(), ncycles=256, vcd_name="my.vcd", keep_files=True) run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True)