Fix axi id width
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bd96b47041
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@ -146,7 +146,7 @@ class VexiiRiscv(CPU):
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "d9917133", args.update_repo)
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "32ec8bd1", args.update_repo)
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if not args.cpu_variant:
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if not args.cpu_variant:
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args.cpu_variant = "standard"
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args.cpu_variant = "standard"
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@ -479,11 +479,13 @@ class VexiiRiscv(CPU):
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self.comb += mbus.aw.lock.eq(0)
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self.comb += mbus.aw.lock.eq(0)
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self.comb += mbus.aw.prot.eq(1)
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self.comb += mbus.aw.prot.eq(1)
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self.comb += mbus.aw.qos.eq(0)
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self.comb += mbus.aw.qos.eq(0)
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#self.comb += mbus.aw.region.eq(0)
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self.comb += mbus.ar.cache.eq(0xF)
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self.comb += mbus.ar.cache.eq(0xF)
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self.comb += mbus.ar.lock.eq(0)
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self.comb += mbus.ar.lock.eq(0)
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self.comb += mbus.ar.prot.eq(1)
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self.comb += mbus.ar.prot.eq(1)
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self.comb += mbus.ar.qos.eq(0)
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self.comb += mbus.ar.qos.eq(0)
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#self.comb += mbus.ar.region.eq(0)
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self.cpu_params.update(
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self.cpu_params.update(
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# Memory Bus (Master).
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# Memory Bus (Master).
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