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Vexii fix mem data width

This commit is contained in:
Dolu1990 2024-06-06 16:36:56 +02:00
parent 0e04949485
commit bd96b47041
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/cpu/vexiiriscv/core.py
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@ -158,8 +158,8 @@ class VexiiRiscv(CPU):
if args.cpu_variant in ["linux", "debian"]:
VexiiRiscv.vexii_args += " --with-rva --with-supervisor"
VexiiRiscv.vexii_args += " --fetch-l1-ways=4"
VexiiRiscv.vexii_args += " --lsu-l1-ways=4"
VexiiRiscv.vexii_args += " --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64"
VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64"
if args.cpu_variant in ["debian"]:
VexiiRiscv.vexii_args += " --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy"