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gen/fhdl/verilog: Simplify/Rename registers initialization parameter.

This commit is contained in:
Florent Kermarrec 2023-05-17 17:23:47 +02:00
parent be1d64acaf
commit 9c890a0a27
1 changed files with 8 additions and 9 deletions
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15
litex/gen/fhdl/verilog.py
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@ -421,7 +421,7 @@ def _print_module(f, ios, name, ns, attr_translate):
return r return r
def _print_signals(f, ios, name, ns, attr_translate, asic=False): def _print_signals(f, ios, name, ns, attr_translate, regs_init):
sigs = list_signals(f) | list_special_ios(f, ins=True, outs=True, inouts=True) sigs = list_signals(f) | list_special_ios(f, ins=True, outs=True, inouts=True)
special_outs = list_special_ios(f, ins=False, outs=True, inouts=True) special_outs = list_special_ios(f, ins=False, outs=True, inouts=True)
inouts = list_special_ios(f, ins=False, outs=False, inouts=True) inouts = list_special_ios(f, ins=False, outs=False, inouts=True)
@ -434,10 +434,10 @@ def _print_signals(f, ios, name, ns, attr_translate, asic=False):
if sig in wires: if sig in wires:
r += "wire " + _print_signal(ns, sig) + ";\n" r += "wire " + _print_signal(ns, sig) + ";\n"
else: else:
if asic: r += "reg " + _print_signal(ns, sig)
r += "reg " + _print_signal(ns, sig) + ";\n" # ASICs can't assign an initial value to a reg, it is always X if regs_init:
else: r += " = " + _print_expression(ns, sig.reset)[0]
r += "reg " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n" r += ";\n"
return r return r
# ------------------------------------------------------------------------------------------------ # # ------------------------------------------------------------------------------------------------ #
@ -532,11 +532,10 @@ def convert(f, ios=set(), name="top", platform=None,
special_overrides = dict(), special_overrides = dict(),
attr_translate = DummyAttrTranslate(), attr_translate = DummyAttrTranslate(),
regular_comb = True, regular_comb = True,
regs_init = True,
# Sim parameters. # Sim parameters.
time_unit = "1ns", time_unit = "1ns",
time_precision = "1ps", time_precision = "1ps",
# Generate for ASIC simulation (i.e. capture X-on-init for regs)
asic = False,
): ):
# Build Logic. # Build Logic.
@ -623,7 +622,7 @@ def convert(f, ios=set(), name="top", platform=None,
# Module Signals. # Module Signals.
verilog += _print_separator("Signals") verilog += _print_separator("Signals")
verilog += _print_signals(f, ios, name, ns, attr_translate, asic) verilog += _print_signals(f, ios, name, ns, attr_translate, regs_init)
# Combinatorial Logic. # Combinatorial Logic.
verilog += _print_separator("Combinatorial Logic") verilog += _print_separator("Combinatorial Logic")