Merge pull request #1690 from bunnie/asic-target
add an option to generate without reg initializers (asic targets)
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commit
be1d64acaf
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@ -421,7 +421,7 @@ def _print_module(f, ios, name, ns, attr_translate):
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return r
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def _print_signals(f, ios, name, ns, attr_translate):
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def _print_signals(f, ios, name, ns, attr_translate, asic=False):
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sigs = list_signals(f) | list_special_ios(f, ins=True, outs=True, inouts=True)
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special_outs = list_special_ios(f, ins=False, outs=True, inouts=True)
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inouts = list_special_ios(f, ins=False, outs=False, inouts=True)
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@ -434,7 +434,10 @@ def _print_signals(f, ios, name, ns, attr_translate):
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if sig in wires:
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r += "wire " + _print_signal(ns, sig) + ";\n"
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else:
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r += "reg " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
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if asic:
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r += "reg " + _print_signal(ns, sig) + ";\n" # ASICs can't assign an initial value to a reg, it is always X
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else:
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r += "reg " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
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return r
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# ------------------------------------------------------------------------------------------------ #
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@ -532,6 +535,8 @@ def convert(f, ios=set(), name="top", platform=None,
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# Sim parameters.
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time_unit = "1ns",
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time_precision = "1ps",
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# Generate for ASIC simulation (i.e. capture X-on-init for regs)
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asic = False,
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):
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# Build Logic.
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@ -618,7 +623,7 @@ def convert(f, ios=set(), name="top", platform=None,
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# Module Signals.
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verilog += _print_separator("Signals")
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verilog += _print_signals(f, ios, name, ns, attr_translate)
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verilog += _print_signals(f, ios, name, ns, attr_translate, asic)
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# Combinatorial Logic.
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verilog += _print_separator("Combinatorial Logic")
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