Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #113 from stffrdhrn/litex-trivial 

Litex trivial
This commit is contained in:
enjoy-digital 2018-10-04 16:25:11 +02:00 committed by GitHub
parent 2be5205463 ff6de429f0
commit 9cf4ffb3f4
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/build/sim/core/libdylib.c
View File

@ -39,7 +39,7 @@ static void set_last_error(const char *s)
if (!s) if (!s)
s = "NULL error"; s = "NULL error";
last_err_set = 1; last_err_set = 1;
strncpy(last_err, s, ERR_MAX_SIZE); strncpy(last_err, s, ERR_MAX_SIZE-1);
} }
static dylib_ref dylib_ref_alloc (void *handle, const char *path) static dylib_ref dylib_ref_alloc (void *handle, const char *path)

2
litex/soc/integration/soc_core.py
View File

@ -384,7 +384,7 @@ class SoCCore(Module):
def soc_core_args(parser): def soc_core_args(parser):
parser.add_argument("--cpu-type", default=None, parser.add_argument("--cpu-type", default=None,
help="select CPU: lm32, mor1kx, picorv32, vexriscv, minerva") help="select CPU: lm32, or1k, picorv32, vexriscv, minerva")
parser.add_argument("--cpu-variant", default=None, parser.add_argument("--cpu-variant", default=None,
help="select CPU variant") help="select CPU variant")
parser.add_argument("--integrated-rom-size", default=None, type=int, parser.add_argument("--integrated-rom-size", default=None, type=int,

2
litex/soc/software/libbase/exception.c
View File

@ -25,7 +25,7 @@ static void emerg_printf(const char *fmt, ...)
} }
} }
static char emerg_getc() static char emerg_getc(void)
{ {
while(uart_rxempty_read()); while(uart_rxempty_read());
char c = uart_rxtx_read(); char c = uart_rxtx_read();