Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

inteconnect/stream: use PipeValid implementation for Buffer

Browse source
This commit is contained in:
Florent Kermarrec 2020-01-30 09:35:40 +01:00
parent 1c88c0f896
commit 9d2894727e
1 changed files with 4 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
litex/soc/interconnect/stream.py
View file

@ -592,19 +592,6 @@ class Monitor(Module, AutoCSR):
underflow_counter = MonitorCounter(reset, latch, ~endpoint.valid & endpoint.ready, self.underflows.status) underflow_counter = MonitorCounter(reset, latch, ~endpoint.valid & endpoint.ready, self.underflows.status)
self.submodules += underflow_counter self.submodules += underflow_counter
# Buffer -------------------------------------------------------------------------------------------
class Buffer(PipelinedActor):
def __init__(self, layout):
self.sink = Endpoint(layout)
self.source = Endpoint(layout)
PipelinedActor.__init__(self, 1)
self.sync += \
If(self.pipe_ce,
self.source.payload.eq(self.sink.payload),
self.source.param.eq(self.sink.param)
)
# Pipe --------------------------------------------------------------------------------------------- # Pipe ---------------------------------------------------------------------------------------------
class PipeValid(Module): class PipeValid(Module):
@ -658,6 +645,10 @@ class PipeReady(Module):
) )
] ]
# Buffer -------------------------------------------------------------------------------------------
class Buffer(PipeValid): pass # FIXME: Replace Buffer with PipeValid in codebase?
# Cast --------------------------------------------------------------------------------------------- # Cast ---------------------------------------------------------------------------------------------
class Cast(CombinatorialActor): class Cast(CombinatorialActor):