platforms/mixxeo: update DVI input timing constraints

2013-11-19 23:15:42 +01:00 · 2013-11-19 23:15:42 +01:00 · 9d5931c969
parent 140ddd31a4
commit 9d5931c969
1 changed files with 1 additions and 1 deletions
--- a/mibuild/platforms/mixxeo.py
+++ b/mibuild/platforms/mixxeo.py
@ -185,7 +185,7 @@ TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
 			try:
 				self.add_platform_command("""
 NET "{dviclk}" TNM_NET = "GRP"""+si+"""";
-TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 26.7 ns HIGH 50%;
+TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 12.00 ns HIGH 50%;
 """, dviclk=self.lookup_request("dvi_in", i).clk_p)
 			except ConstraintError:
 				pass