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cpu/femtorv/firev: Remove debug displays now that validated in sim and hardware.

This commit is contained in:
Florent Kermarrec 2022-03-09 10:54:05 +01:00
parent ece286b15d
commit 9d5bf70cb2
2 changed files with 0 additions and 22 deletions
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12
litex/soc/cores/cpu/femtorv/core.py
View File

@ -147,18 +147,6 @@ class FemtoRV(CPU):
self.comb += mbus.rdata.eq(mbus_rdata) # Latched value.
self.comb += If(latch, mbus.rdata.eq(idbus.dat_r)) # Immediate value.
# Main Ram accesses debug.
if False:
self.sync += If(mbus.addr[28:32] == 0x4, # Only Display Main Ram accesses.
If(idbus.stb & idbus.ack,
If(idbus.we,
Display("Write: Addr 0x%08x : Data 0x%08x, Sel: 0x%x", idbus.adr, idbus.dat_w, idbus.sel)
).Else(
Display("Read: Addr 0x%08x : Data 0x%08x", idbus.adr, idbus.dat_r)
)
)
)
# Add Verilog sources.
# --------------------
self.add_sources(platform, variant)

10
litex/soc/cores/cpu/firev/core.py
View File

@ -120,16 +120,6 @@ class firev(CPU):
mbus.in_ram_data_out.eq(idbus.dat_r),
mbus.in_ram_done.eq(idbus.ack),
]
# Main Ram accesses debug.
if False:
self.sync += If(idbus.stb & idbus.ack,
If(idbus.we,
Display("Write: Addr 0x%08x : Data 0x%08x, Sel: 0x%x", idbus.adr, idbus.dat_w, idbus.sel)
).Else(
Display("Read: Addr 0x%08x : Data 0x%08x", idbus.adr, idbus.dat_r)
)
)
# Add Verilog sources.
# --------------------