Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

build/xilinx/XilinxMultiRegImpl: fix n=0 case

Browse source
This commit is contained in:
Florent Kermarrec 2019-12-16 11:12:38 +01:00
parent ec7dc2d8f4
commit 9da28c4ea5
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
litex/build/xilinx/common.py
View file

@ -78,7 +78,8 @@ class XilinxMultiRegImpl(MultiRegImpl):
if not hasattr(i, "attr"):
i0, i = i, Signal()
self.comb += i.eq(i0)
self.regs[0].attr.add("mr_ff")
if len(self.regs):
self.regs[0].attr.add("mr_ff")
for r in self.regs:
r.attr.add("async_reg")
r.attr.add("no_shreg_extract")