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build/xilinx/XilinxMultiRegImpl: fix n=0 case

This commit is contained in:
Florent Kermarrec 2019-12-16 11:12:38 +01:00
parent ec7dc2d8f4
commit 9da28c4ea5
1 changed files with 2 additions and 1 deletions
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litex/build/xilinx/common.py
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@ -78,6 +78,7 @@ class XilinxMultiRegImpl(MultiRegImpl):
if not hasattr(i, "attr"): if not hasattr(i, "attr"):
i0, i = i, Signal() i0, i = i, Signal()
self.comb += i.eq(i0) self.comb += i.eq(i0)
if len(self.regs):
self.regs[0].attr.add("mr_ff") self.regs[0].attr.add("mr_ff")
for r in self.regs: for r in self.regs:
r.attr.add("async_reg") r.attr.add("async_reg")