build/xilinx/XilinxMultiRegImpl: fix n=0 case

2019-12-16 11:12:38 +01:00 · 2019-12-16 11:12:38 +01:00 · 9da28c4ea5
parent ec7dc2d8f4
commit 9da28c4ea5
1 changed files with 2 additions and 1 deletions
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@ -78,7 +78,8 @@ class XilinxMultiRegImpl(MultiRegImpl):
        if not hasattr(i, "attr"):
            i0, i = i, Signal()
            self.comb += i.eq(i0)
-        self.regs[0].attr.add("mr_ff")
+        if len(self.regs):
+            self.regs[0].attr.add("mr_ff")
        for r in self.regs:
            r.attr.add("async_reg")
            r.attr.add("no_shreg_extract")