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Added Vexriscv hardware breakpoint variants for Mini and Lite.

This commit is contained in:
Mikolaj Sowinski 2022-01-24 00:00:26 +01:00
parent 8d3f12ebbd
commit 9e0d8b3f41
1 changed files with 19 additions and 17 deletions
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litex/soc/cores/cpu/vexriscv/core.py
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@ -24,8 +24,10 @@ from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
CPU_VARIANTS = { CPU_VARIANTS = {
"minimal": "VexRiscv_Min", "minimal": "VexRiscv_Min",
"minimal+debug": "VexRiscv_MinDebug", "minimal+debug": "VexRiscv_MinDebug",
"minimal+debug+hwbp": "VexRiscv_MinDebugHwBP",
"lite": "VexRiscv_Lite", "lite": "VexRiscv_Lite",
"lite+debug": "VexRiscv_LiteDebug", "lite+debug": "VexRiscv_LiteDebug",
"lite+debug+hwbp": "VexRiscv_LiteDebugHwBP",
"standard": "VexRiscv", "standard": "VexRiscv",
"standard+debug": "VexRiscv_Debug", "standard+debug": "VexRiscv_Debug",
"imac": "VexRiscv_IMAC", "imac": "VexRiscv_IMAC",