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fhdl/verilog: Fix sig.direction regression.

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This commit is contained in:
Florent Kermarrec 2021-10-31 23:40:11 +01:00
parent 3ba5d6f187
commit 9ecb1e61a9
1 changed files with 1 additions and 1 deletions
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2
litex/gen/fhdl/verilog.py
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@ -395,7 +395,7 @@ def _print_module(f, ios, name, ns, attr_translate):
sig.direction = "inout" sig.direction = "inout"
r += "\tinout wire " + _print_signal(ns, sig) r += "\tinout wire " + _print_signal(ns, sig)
elif sig in targets: elif sig in targets:
sig.direction = "output " sig.direction = "output"
if sig in wires: if sig in wires:
r += "\toutput wire " + _print_signal(ns, sig) r += "\toutput wire " + _print_signal(ns, sig)
else: else: