Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

fhdl/verilog: Fix sig.direction regression.

Browse source
This commit is contained in:
Florent Kermarrec 2021-10-31 23:40:11 +01:00
parent 3ba5d6f187
commit 9ecb1e61a9
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/gen/fhdl/verilog.py
View file

@ -395,7 +395,7 @@ def _print_module(f, ios, name, ns, attr_translate):
sig.direction = "inout"
r += "\tinout wire " + _print_signal(ns, sig)
elif sig in targets:
sig.direction = "output "
sig.direction = "output"
if sig in wires:
r += "\toutput wire " + _print_signal(ns, sig)
else: