tools: move from litex.soc.tools to litex.tools and fix usb.core import

litex/__init__.py

@@ -1 +1 @@
-from litex.soc.tools.remote import RemoteClient
+from litex.tools.litex_client import RemoteClient

litex/soc/software/bios/Makefile

@@ -16,9 +16,9 @@ ifneq ($(OS),Windows_NT)
 	chmod -x $@
 endif
 ifeq ($(CPUENDIANNESS),little)
-	$(PYTHON) -m litex.soc.tools.mkmscimg $@ --little
+	$(PYTHON) -m litex.soc.software.mkmscimg $@ --little
 else
-	$(PYTHON) -m litex.soc.tools.mkmscimg $@
+	$(PYTHON) -m litex.soc.software.mkmscimg $@
 endif
 
 bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS)

litex/soc/tools/remote/__init__.py

@@ -1,5 +0,0 @@
-from litex.soc.tools.remote.comm_uart import CommUART
-from litex.soc.tools.remote.comm_udp import CommUDP
-from litex.soc.tools.remote.comm_pcie import CommPCIe
-from litex.soc.tools.remote.comm_usb import CommUSB
-from litex.soc.tools.remote.litex_client import RemoteClient

litex/tools/litex_client.py

@@ -1,9 +1,9 @@
 import socket
 
-from litex.soc.tools.remote.etherbone import EtherbonePacket, EtherboneRecord
-from litex.soc.tools.remote.etherbone import EtherboneReads, EtherboneWrites
-from litex.soc.tools.remote.etherbone import EtherboneIPC
-from litex.soc.tools.remote.csr_builder import CSRBuilder
+from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord
+from litex.tools.remote.etherbone import EtherboneReads, EtherboneWrites
+from litex.tools.remote.etherbone import EtherboneIPC
+from litex.tools.remote.csr_builder import CSRBuilder
 
 
 class RemoteClient(EtherboneIPC, CSRBuilder):

litex/tools/litex_server.py

@@ -7,8 +7,8 @@ import socket
 import time
 import threading
 
-from litex.soc.tools.remote.etherbone import EtherbonePacket, EtherboneRecord, EtherboneWrites
-from litex.soc.tools.remote.etherbone import EtherboneIPC
+from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord, EtherboneWrites
+from litex.tools.remote.etherbone import EtherboneIPC
 
 
 class RemoteServer(EtherboneIPC):
@@ -136,7 +136,7 @@ def main():
 
 
     if args.uart:
-        from litex.soc.tools.remote import CommUART
+        from litex.tools.remote import CommUART
         if args.uart_port is None:
             print("Need to specify --uart-port, exiting.")
             exit()
@@ -145,13 +145,13 @@ def main():
         print("[CommUART] port: {} / baudrate: {} / ".format(uart_port, uart_baudrate), end="")
         comm = CommUART(uart_port, uart_baudrate)
     elif args.udp:
-        from litex.soc.tools.remote import CommUDP
+        from litex.tools.remote import CommUDP
         udp_ip = args.udp_ip
         udp_port = int(args.udp_port)
         print("[CommUDP] ip: {} / port: {} / ".format(udp_ip, udp_port), end="")
         comm = CommUDP(udp_ip, udp_port)
     elif args.pcie:
-        from litex.soc.tools.remote import CommPCIe
+        from litex.tools.remote import CommPCIe
         pcie_bar = args.pcie_bar
         if args.pcie_bar is None:
             print("Need to speficy --pcie-bar, exiting.")
@@ -159,7 +159,7 @@ def main():
         print("[CommPCIe] bar: {} / ".format(args.pcie_bar), end="")
         comm = CommPCIe(args.pcie_bar)
     elif args.usb:
-        from litex.soc.tools.remote import CommUSB
+        from litex.tools.remote import CommUSB
         if args.usb_pid is None and args.usb_vid is None:
             print("Need to speficy --usb-vid or --usb-pid, exiting.")
             exit()

litex/tools/remote/comm_udp.py

@@ -1,7 +1,7 @@
 import socket
 
-from litex.soc.tools.remote.etherbone import EtherbonePacket, EtherboneRecord
-from litex.soc.tools.remote.etherbone import EtherboneReads, EtherboneWrites
+from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord
+from litex.tools.remote.etherbone import EtherboneReads, EtherboneWrites
 
 
 class CommUDP:

setup.py

@@ -36,11 +36,10 @@ setup(
     include_package_data=True,
     entry_points={
         "console_scripts": [
-            "mkmscimg=litex.soc.tools.mkmscimg:main",
-            "litex_term=litex.utils.litex_term:main",
-            "litex_server=litex.utils.litex_server:main",
-            "litex_sim=litex.utils.litex_sim:main",
-            "litex_read_verilog=litex.utils.litex_read_verilog:main",
+            "litex_term=litex.tools.litex_term:main",
+            "litex_server=litex.tools.litex_server:main",
+            "litex_sim=litex.tools.litex_sim:main",
+            "litex_read_verilog=litex.tools.litex_read_verilog:main",
             "litex_simple=litex.boards.targets.simple:main",
         ],
     },