Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

udp/crossbar: add possibility to get port with dw != 8 (16, 32, 64, ...)

This commit is contained in:
Florent Kermarrec 2015-02-10 11:22:23 +01:00
parent 4e8e1dd8b1
commit 9f91348c1c
3 changed files with 31 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
liteeth/core/ip/crossbar.py
View File

@ -11,9 +11,9 @@ class LiteEthIPV4Crossbar(Module):
self.master = LiteEthIPV4MasterPort(8)
def get_port(self, protocol):
port = LiteEthIPV4UserPort(8)
if protocol in self.users.keys():
raise ValueError("Protocol {0:#x} already assigned".format(protocol))
port = LiteEthIPV4UserPort(8)
self.users[protocol] = port
return port

24
liteeth/core/udp/crossbar.py
View File

@ -10,12 +10,28 @@ class LiteEthUDPCrossbar(Module):
self.users = OrderedDict()
self.master = LiteEthUDPMasterPort(8)
def get_port(self, udp_port):
port = LiteEthUDPUserPort(8)
def get_port(self, udp_port, dw=8):
if udp_port in self.users.keys():
raise ValueError("Port {0:#x} already assigned".format(udp_port))
self.users[udp_port] = port
return port
user_port = LiteEthUDPUserPort(dw)
internal_port = LiteEthUDPUserPort(8)
if dw != 8:
converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8))
self.submodules += converter
self.comb += [
Record.connect(user_port.sink, converter.sink),
Record.connect(converter.source, internal_port.sink)
]
converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw))
self.submodules += converter
self.comb += [
Record.connect(internal_port.source, converter.sink),
Record.connect(converter.source, user_port.source)
]
self.users[udp_port] = internal_port
else:
self.users[udp_port] = user_port
return user_port
def do_finalize(self):
# TX arbitrate

17
liteeth/test/udp_tb.py
View File

@ -13,7 +13,8 @@ ip_address = 0x12345678
mac_address = 0x12345678abcd
class TB(Module):
def __init__(self):
def __init__(self, dw=8):
self.dw = dw
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
@ -21,15 +22,15 @@ class TB(Module):
self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True)
self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
udp_port = self.core.udp.crossbar.get_port(0x5678)
self.submodules.streamer = PacketStreamer(eth_udp_user_description(8))
self.submodules.logger = PacketLogger(eth_udp_user_description(8))
udp_port = self.core.udp.crossbar.get_port(0x5678, dw)
self.submodules.streamer = PacketStreamer(eth_udp_user_description(dw))
self.submodules.logger = PacketLogger(eth_udp_user_description(dw))
self.comb += [
Record.connect(self.streamer.source, udp_port.sink),
udp_port.sink.ip_address.eq(0x12345678),
udp_port.sink.src_port.eq(0x1234),
udp_port.sink.dst_port.eq(0x5678),
udp_port.sink.length.eq(64),
udp_port.sink.length.eq(64//(dw//8)),
Record.connect(udp_port.source, self.logger.sink)
]
@ -54,7 +55,7 @@ class TB(Module):
yield
while True:
packet = Packet([i for i in range(64)])
packet = Packet([i for i in range(64//(self.dw//8))])
yield from self.streamer.send(packet)
yield from self.logger.receive()
@ -64,4 +65,6 @@ class TB(Module):
if __name__ == "__main__":
run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
run_simulation(TB(8), ncycles=2048, vcd_name="my.vcd", keep_files=True)
run_simulation(TB(16), ncycles=2048, vcd_name="my.vcd", keep_files=True)
run_simulation(TB(32), ncycles=2048, vcd_name="my.vcd", keep_files=True)