udp/crossbar: add possibility to get port with dw != 8 (16, 32, 64, ...)
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@ -11,9 +11,9 @@ class LiteEthIPV4Crossbar(Module):
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self.master = LiteEthIPV4MasterPort(8)
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self.master = LiteEthIPV4MasterPort(8)
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def get_port(self, protocol):
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def get_port(self, protocol):
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port = LiteEthIPV4UserPort(8)
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if protocol in self.users.keys():
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if protocol in self.users.keys():
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raise ValueError("Protocol {0:#x} already assigned".format(protocol))
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raise ValueError("Protocol {0:#x} already assigned".format(protocol))
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port = LiteEthIPV4UserPort(8)
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self.users[protocol] = port
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self.users[protocol] = port
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return port
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return port
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@ -10,12 +10,28 @@ class LiteEthUDPCrossbar(Module):
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self.users = OrderedDict()
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self.users = OrderedDict()
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self.master = LiteEthUDPMasterPort(8)
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self.master = LiteEthUDPMasterPort(8)
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def get_port(self, udp_port):
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def get_port(self, udp_port, dw=8):
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port = LiteEthUDPUserPort(8)
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if udp_port in self.users.keys():
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if udp_port in self.users.keys():
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raise ValueError("Port {0:#x} already assigned".format(udp_port))
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raise ValueError("Port {0:#x} already assigned".format(udp_port))
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self.users[udp_port] = port
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user_port = LiteEthUDPUserPort(dw)
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return port
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internal_port = LiteEthUDPUserPort(8)
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if dw != 8:
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converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8))
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self.submodules += converter
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self.comb += [
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Record.connect(user_port.sink, converter.sink),
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Record.connect(converter.source, internal_port.sink)
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]
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converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw))
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self.submodules += converter
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self.comb += [
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Record.connect(internal_port.source, converter.sink),
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Record.connect(converter.source, user_port.source)
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]
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self.users[udp_port] = internal_port
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else:
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self.users[udp_port] = user_port
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return user_port
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def do_finalize(self):
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def do_finalize(self):
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# TX arbitrate
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# TX arbitrate
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@ -13,7 +13,8 @@ ip_address = 0x12345678
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mac_address = 0x12345678abcd
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mac_address = 0x12345678abcd
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class TB(Module):
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class TB(Module):
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def __init__(self):
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def __init__(self, dw=8):
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self.dw = dw
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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@ -21,15 +22,15 @@ class TB(Module):
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self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True)
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self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True)
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self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
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self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
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udp_port = self.core.udp.crossbar.get_port(0x5678)
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udp_port = self.core.udp.crossbar.get_port(0x5678, dw)
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self.submodules.streamer = PacketStreamer(eth_udp_user_description(8))
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self.submodules.streamer = PacketStreamer(eth_udp_user_description(dw))
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self.submodules.logger = PacketLogger(eth_udp_user_description(8))
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self.submodules.logger = PacketLogger(eth_udp_user_description(dw))
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self.comb += [
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self.comb += [
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Record.connect(self.streamer.source, udp_port.sink),
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Record.connect(self.streamer.source, udp_port.sink),
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udp_port.sink.ip_address.eq(0x12345678),
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udp_port.sink.ip_address.eq(0x12345678),
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udp_port.sink.src_port.eq(0x1234),
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udp_port.sink.src_port.eq(0x1234),
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udp_port.sink.dst_port.eq(0x5678),
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udp_port.sink.dst_port.eq(0x5678),
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udp_port.sink.length.eq(64),
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udp_port.sink.length.eq(64//(dw//8)),
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Record.connect(udp_port.source, self.logger.sink)
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Record.connect(udp_port.source, self.logger.sink)
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]
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]
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@ -54,7 +55,7 @@ class TB(Module):
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yield
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yield
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while True:
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while True:
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packet = Packet([i for i in range(64)])
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packet = Packet([i for i in range(64//(self.dw//8))])
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yield from self.streamer.send(packet)
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yield from self.streamer.send(packet)
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yield from self.logger.receive()
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yield from self.logger.receive()
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@ -64,4 +65,6 @@ class TB(Module):
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if __name__ == "__main__":
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(8), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(16), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(32), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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